Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

PIO address space

Altera_Forum
Honored Contributor II
1,224 Views

Hello! 

 

May be somebody knows, why SOPC Builder determins 0x0F address space for every PIO? Why does PIO need such size of address space? 

 

Tnank you.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
537 Views

Hi Kira, 

 

The PIO is always generated with two address bits. For I/O, 

the registers are 32-bit aligned. So you get 4 regs x 4 bytes 

or 0x10 of address space -- even when some of the registers 

are not implemented (e.g. write-only PIO).  

 

Regards, 

--Scott
0 Kudos
Reply