Intel N100 design issues

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Intel N100 design issues

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My customer have the design back from manufacturing. The design is very similar to the DDR5 CRB but they are counting on the VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05 to be supplied from the CPU FIVR.

For now they don't see that the processor is executing any BIOS code at all; although they see SPI flash transactions showing that the PCH at least is alive.

The question that they have for now is how configure the CPU Straps to use the CPU FIVR to supply VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05?

Please refer to the snippet from the schematics that processor CC34/CD34 are shorted and CA28/CC28 are shorted without being externally supplied.

they also got the Intel modular flash tool and they see how to configure VCCANA from FIVR; but we do not see how to do that for VCC_VNNEXT and VCC_V1P05EXT as below -

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