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Altera_Forum
Honored Contributor I
848 Views

125 MHz clock+data output

I have a design with a CycloneIV that needs to talk to a GMII PHY, which expects data bytes on 8 parallel lines along with a clock signal. 

 

I use a PLL to generate a 125 MHz clock, and would now like to route that to an output pin. The primitive approach gives warnings: 

 

Warning (15058): PLL "ethernet_pll:ethernet_pll|altpll:altpll_component|ethernet_pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins 

Warning (15064): PLL "ethernet_pll:ethernet_pll|altpll:altpll_component|ethernet_pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "eth_tx_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance 

 

The second warning is obvious -- I'm trying to get a clock to an output pin, which is a bad idea, that's what CLKOUT pins are for. However, if I set the pin mode, then I lose synchronization in the VHDL model between the output pin and the data bus, because now the fitter is unaware that these should be synchronized. 

 

It appears that there is also no phase compensation mode for this case either -- I can make the PLL synchronize either the output pin or the internal clock distribution to the input clock, but if I understood correctly, I'd need both in order to get predictable behavior. 

 

So, how do I generate both a clock and a parallel data bus at the same time?
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Altera_Forum
Honored Contributor I
42 Views

Have you looked at this guide: https://www.altera.com/en_us/pdfs/literature/ug/ug_altddio.pdf on using the DDR I/O macro functions?

Altera_Forum
Honored Contributor I
42 Views

Excellent, this is pretty much what I need (except now I get to hunt segmentation faults in MegaWizard). 

 

Thanks!
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