Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Comunicados
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussões

A10 DSP Core Timing Error

Altera_Forum
Colaborador honorário II
1.502 Visualizações

Hi All, 

 

I have a problem about Arria10 Chip MPDSP Core in my design. A path from register to MPDSP's ax[30] pin timing violate, 

Then I used TimeQuest Timing Analyzer report this path and found that MPDSP's ax[30] pin setup time(uTsu)=2.955 ns. 

Why this uTsu so long ? 

The Timing analysis as post picture! 

 

pofeng1885 

shenh@innorise.cn
0 Kudos
1 Responder
Altera_Forum
Colaborador honorário II
776 Visualizações

Hi, 

Can you locate the ax[30], or the path including launched from ax[30] in Technology map viewer? 

You can do right-click on the cell of the Time Quest table, and select the Locate-path -> Technology map viewer. 

I would like to know what resources is the path mapped to on the chip. 

 

Mickycat
Responder