Hello I have hold timing issue on the ALTLVDS RX inside logic ..
I have an ALTLVDS RX ip confgiured like that
i get hold timing issues in timequest :
-0.019 u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.serdes_dpa_inst~rx_internal_reg u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.des[4].rxout_ufi~ufi_write_reg u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_fclk0 u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_loaden0
why its occur ? its inside the altera IP ..
Thx
kikoss
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Hello,
We have tried creating an example design with the parameters shown and saw no timing failures. The worst-case slack for the timing path listed was 2.853.
The large discrepancy between the slack we are seeing and the slack you are seeing is mostly likely due to you having a different clock relationship because their PLL clocks are configured incorrectly.
Ensure that the VCO frequency and the outclk frequency/phase shift/duty cycle settings on the external PLL driving the LVDS IP match the settings listed in the Clock Resource Summary in the LVDS IP.
Also, please ensure that the reference clock frequency on the PLL IP matches the Actual inclock frequency on the LVDS IP as the settings listed in the Clock Resource Summary tab may not be attainable with the wrong reference clock frequency.
Regards,
Aqid
I reduce my design to the minimum.
And seems that the issue occurs when we choose more than 2 channels
when running with 2 channels, no timing issue, when running with 3 channels, I get hold time issue ...
@AqidAyman_Intel seems there its an altera issue ..
wait for help from @altera ..
THX
kikoss
