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I had the following in my design:
r_reg1 <= { r_reg1, inputpin };
Then I had to introduce a condition to select which register input data will be shifted into, I did it this way: if(r_condition)
r_reg1 <= { r_reg1, inputpin };
else r_reg2 <= { r_reg2, inputpin };
And my project stops compiling because Quartus tries to use another M9K block for Altshift_Tabs megafunction, and all the RAM blocks are already in use. Why Quartus is doing it? Why it does not do what it was instructed to do - just use two registers and shift input data in respective one on the condition? Please advise. Thank you.
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I found the solution.
Assignments -> Settings -> Analysis & Synthesis settings -> Auto shift register replacement=OFF. --- Quote Start --- To infer shift registers, synthesis tools detect a group of shift registers of the samelength and convert them to an ALTSHIFT_TAPS megafunction. To be detected, all theshift registers must have the following characteristics: ■ Use the same clock and clock enable ■ Do not have any other secondary signals ■ Have equally spaced taps that are at least three registers apart --- Quote End --- --- Quote Start --- If theAuto Shift Register Recognition setting is set to Auto, Quartus II integratedsynthesis uses the Optimization Technique setting, logic and RAM utilizationinformation about the design, and timing information from Timing-Driven Synthesisto determine which shift registers are implemented in RAM blocks for logic. --- Quote End --- From the Altera's guide "6. Recommended HDL Coding Styles".- Mark as New
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If you're happy to leave it global, thats fine - but you can set that setting per module - either in the assignments editor or modifying the .qsf file by hand.
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