Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

[Nicole04]

Good day,

I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the old EMIF IP with the HPS EMIF IP (emif_io96b_hps). 

I can generate the HDL from Platform Designer without any errors. I get the following error when compiling:

Error(17821): Netlist error at hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd(275): port 's1_axi4_wuser' of width 64 cannot connect to actual of width 32

Details:

• Quartus 24.3.1 is used with all IP upgraded.
• I connect the io96b0_to_hps conduits of the HPS and HPS EMIF together. 
• The channel 1 axi4 wuser is 32 bits wide for both the HPS and EMIF:
  
  
• I am using LPDDR4 with configuration of 2x16 (8Gbit).
• In hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd the wuser signals are all of width 32.

I am unable to see where the 64-bit wide signal is and how to fix it.

C:/Firmware/CheetahTacticalRouter/tactical-router-fw/tactical_router_fpga/quartus/ip/hps_system/hps_system_emif_io96b/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/synth/ip/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4/synth/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd

[Nicole04]

Hi Adzim,

Thank you for looking into this problem. I see multiple files containing this portion. Should it be changed at all cases? 

I changed it at all places and then received the following error:
Error(13224): Verilog HDL or VHDL error at io0_emif_bank2a_fpga_emif_io96b_lpddr4_200_tq2i7vi_atom_inst_hmc_wide.sv(1041): index 32 is out of range [31:0] for 'ruser'

Kind regards,

Nicole

[Nicole04]

Hi Adzim,

Thank you for the update. Will an IP core update be made? 

My one design works, but another gives a file inclusion error:
Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4_emif_io96b_cal_200_hpbproa.sv(17): cannot open include file cal_io96b_interface.svh

Kind regards,

Nicole

[AdzimZM_Intel]

Hi Nicole,

I don't think you need to change in all files.

Make the change in the top IP file should be okay.

Try to regenerate the IP file again and make the change in the path that I have provided.

Regards,

Adzim

[Nicole04]

Hi Adzim,

The width error seems to be fixed in the Quartus 25.1 version.

I do however still get the inclusion error. I have tried regenerating the IP, cleaning the project and regenerating again, but the error persists. The included file does exist.

Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_300_4hwut5y_emif_0_lpddr4_emif_io96b_lpddr4_300_ljjag6i.sv(17): cannot open include file emif_io96b_interface.svh

Kind regards,

Nicole

[Nicole04]

I was able to get a temporary work around, but hopefully this can be fixed in the future.

I was able to compile the design when the path is made shorter. I had to place my quartus folder directly on the C drive of my PC, because the path for the LPDDR4 EMIF IP is very long. 

Is there a way to shorten the names used in the IP folders?

[AdzimZM_Intel]

Hi Nicole,

I'm glad that your issue has been resolved.

We will try to improve the IP file name to avoid this issue in future.

Currently we cannot set the IP file name shorter automatically.

Manually edit the IP file name is possible.

Regards,

Adzim