Are the LVDS terminations react on Pins in which no signal pass ?

[Altera_Forum]

Hi, 

 I run simulation of cyclone 5 LVDS signal in Hyperlynx SI using IBIS model created by Quartus compilation.  According to the Assignment Editor/PinPlanner the input termination on that pin was marked as "YES" so there supposed to be a 100 ohm differential termination on that diff pair pin .  The simulation looks bad as there is no termination there.   Does the fact that there is no signal running on that Pin in the VHDL code may cause that the termination is not realy activated eventhough the input terminations of these Pins were marked in the Assignment Editor "YES" ?    Thanks

[Altera_Forum]

You can observe that Quartus doesn't place a LVDS input without a respective input port. Do you say, the termination isn't connected although the pin is defined as input port, but not driving actual logic? Which FPGA family?

[Altera_Forum]

--- Quote Start ---  You can observe that Quartus doesn't place a LVDS input without a respective input port. Do you say, the termination isn't connected although the pin is defined as input port, but not driving actual logic? Which FPGA family?  --- Quote End ---    Yes, that's exactly what I meant.   FPGA Family : Cyclone V GX C5 F27 Grade 7 Manufacturer Part Number - 5CGXFC5C6F27C7N.

[Altera_Forum]

I was yet under the impression that the differential termination is activated in this case, but I didn't measure it. May be it's an IBIS model bug?

[Altera_Forum]

I see lvds_crin_t100 and lvds_rrin_t100 referenced in .ibs model for the terminated Cyclone 5 LVDS inputs, with or without connected logic. Did you check your IBIS file?

[Altera_Forum]

--- Quote Start ---  I see lvds_crin_t100 and lvds_rrin_t100 referenced in .ibs model for the terminated Cyclone 5 LVDS inputs, with or without connected logic. Did you check your IBIS file?  --- Quote End ---    Yes, I have already checked it before and "lvds_crin_t100" is written near each of the diff pins in the IBIS model.