Avalon mm pipeline bridge problem: multible write

[CAlex]

Hi,

Im using CycloneVsoc link lwh2f(32bit) ---> Avalon mm pipeline bridge(32bit) -----> MyIP core(8bit)

the following is the signal tap result:

When I ran alt_write_byte for one time in the timer IRQ.

Here is my verilog logic:

The port reset_wr here should be only one pulse signal when I wrote to the FPGA module.

The other problem is that writedata signal should be at 0b01---->0b11------->0b01------> loop

yet signal tap didnt catch the value.

It change from 01 to 00 for severial times.

Writedata[1] should be at 0 until I write.

Could you please help me with that?

Thank you.

Reguards

Alex

[sstrell]

You don't specify in your HDL what irq_en should be when write is low, so you've basically created a latch.

But I don't understand why in your Signal Tap capture writedata[1] does not match what is shown for writedata[7..0].  Are you sure you are tapping the correct signals or accidentally tapping a different writedata[1]?

[CAlex]

Hi

irq_en is what I want to have,

reset_wr signal is not, I didnt expect 4 write signal when using alt_write_byte().

And yes, they are the same signal, which makes this case stranger.

[sstrell]

You do not want to have a latch, especially in an FPGA design.  They make it difficult to meet timing and can cause glitching.  That could be part of this problem depending on how irq_en is working with the rest of the design.

As for the weird writedata, I'd try removing and re-adding the signals in the .stp file or just create a brand new .stp in case the file is corrupt.

[CAlex]

Thank you,

I'd have a try.

[CAlex]

Hi，Sstrell

Since you mentioned on the latch problem,

do you mind sharing how you handle level-sensitive registers?

what Im trying to do is that irq_signal = irq_en & reset_assert.

irq_en should always be 1(if I write 1) until I write 0.

Thank you very much

[sstrell]

assign irq_signal = irq_en & reset_assert;

always @(posedge clk or negedge reset_n)
begin
     if (reset_n == 1'b0)
          irq_en <= 1'b0;
     else if (write)
          if (writedata[0])
               irq_en <= 1'b1;
          else
               irq_en <= 1'b0;

Your "write" signal is essentially a synchronous clock enable for the register and writedata[0] is a synchronous set.  You just have to cover both cases for it.  This should now synthesize correctly.

[CAlex]

THANK YOU,

if you dont mind , I'll add that into my design.

[CAlex]

And about the mult write problem, Ive created a new stp, but the problem still exist.

Have you ever meat this knid of wield problem before?

Tnak you again for your help.