Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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19997 Discussions

Basic example of lpm_counter1 disabled when in overflow

Honored Contributor II

Hi all I need to have a counter that when overflows is set to a predefined value and stops counting. Then only an external signal of clear can restart (from 0) the counter.  

I thought to use the carry out of lpm_counter1 to disable the counter and a DFF to store carry out until a synchronous clear arrives. 

The carry out is also used as a synchronous set for the counter.  

From the simulation the DFF does not behave as expected and it changes its output not following its input nor clock... 

I attach here a screenshot of design and simulation. 

I would be glad you could give me some suggestions.. 

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2 Replies
Honored Contributor II

carry_out (the overflow) never goes high because you're clearing the counter before it ever has a chance to, at least in the simulation waveform you show here. Since you're using it as the clock for the dff (a big no-no since you're creating a gated clock; put it on clock enable for the dff instead), the output of the dff is dictated only by the A_clear signal.

Honored Contributor II

I jumped to same conclusion but indeed I was not able to find a solution to that! 

Now thanks to you it is showed here: DFFE!  

Thanks a lot