Best practices for assigning related pins in pin planner?

[frwo]

Hi @ll!

I'd like to know if or when it's necessary or even recommended to assign related pins (e.g. the lines of an address bus, data bus etc.) to the same I/O bank (or I/O banks with same settings) OR if I can use whatever pin I want to to make the PCB design easier?!

Thanks, Frank

[sstrell]

In general, you can use whichever available GPIO pins you want as long as you follow all the pin placement guidelines of the device (checked automatically during compilation or manually if you perform an I/O Assignment Analysis). The key thing to be concerned about, though, would be timing. You don't mention your device or how far you might be spreading these bus pins, but you want to make sure that you still meet your I/O timing requirements, and that means properly setting up a .sdc file and performing a timing analysis. Check out the timing analyzer user guide for details: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html

#iwork4intel

[frwo]

Thanks for your answer. I use a MAX10 device and whenever possible I try to use adjacent pins for related bus pins or even group them to one specific I/O bank. Sometimes it's just easiier to use an adjacent pin/port which is in another bank but eases PCB layout a lot. That's why I asked. 😊