I’m looking for some help to constraint my design. I didn’t write constraint before and i look some documents on internet. Still can’t find any example similar to my design.
My design has two interface protocol, the two interface will use the same ports to output to external device. Each interface has it’s own clock and data. So i use mux to decide which signal will be sent.
The code looks like :
//ifsel=1 : interface1. ifsel=0 : interface2.
assign portA = (ifsel)?(interface1_data1):(interface2_clock) ;
assign portB = (ifsel)?(interface1_data2):(interface2_data1) ;
assign portC = (ifsel)?(interface1_data3):(interface2_data2) ;
assign portD = (ifsel)?(interface1_clock):(interface2_data3) ;
The external device needs setup and hold time as following.
interface 1 : setup time : 1.7ns, hold time : 1.6ns (reference to interface1_clock rising edge, interface1_clock needs 180 MHz)
interface 2 : setup time : 1.5ns, hold time : 1.4ns (reference to interface2_clock rising edge, interface2_clock needs 160 MHz)
In this situation, how to set output constraint?
You're essentially creating a source synchronous single data rate (SDR) output interface. There's quite a few constraints involved, so check out this training first:
You'll need a generated output clock constraint, output delay constraints, a false path constraint for the clock, and potentially a multicycle exception. Post again if you want a check of your code after seeing the training.
Thanks for your information.
After the on-line training, i have learned some skill for setting constraint source synchronous system.
But i still have a question.
The train class shows the FPGA ports are only one use.( clock port is clock, data port is data)
In my design, i have two different source synchronous signals will use the same ports.
FPGA port will be clock pin or data pin for different interface.
ex : port A is not only the data1 of interface1, but also the clock of interface2.
portD is not only the clock of interface 1, but also the data3 of interface2.
How to set two different desired constraint on the same FPGA port?