CMOS General Input Output (IO) pin speed specification of cyclone IV

[Altera_Forum]

Hi, 

 We want to connect 3.3V 125MHz CMOS signal to one of the banks of Cyclone -IV FPGA EP4CE30F23C8N. .  We want to know the maximum IO speed specification of this device ?   Regards, Thulasi

[Altera_Forum]

You can connect that sort of signal to any of the I/O banks. Best design practice will recommend that you power that bank from a 3.3V supply as well. 

 The bigger question is - what do you want to do with that CMOS signal. If you do nothing with it the device will quite happily 'operate' at 125MHz.  Assuming it is a clock with which you intend to drive logic, then if that logic becomes complicated the device may not meet timing and therefore may not run correctly at 125MHz.  The slowest speed grade Cyclone IV devices will quite happily drive well designed logic at 125MHz.

[Altera_Forum]

Hi, 

 Thanks for your reply. But, I would like to know, maximum IO frequency of 3.3V LVCMOS in cyclone IV. Please mention where is it specified in the data sheet/handbook ? In page 471 of hand book it is mentioned as "The maximum I/O frequency is different for each I/O standard". I would like to know the maximum I/O frequency of 3.3 LVCMOS being supported by cyclone IV FPGA. Please help.  Regards, Thulasi

[Altera_Forum]

Refer to chapter 1 of the 'Cyclone IV Device Datasheet': 

http://www.altera.co.uk/literature/hb/cyclone-iv/cyiv-53001.pdf (http://www.altera.co.uk/literature/hb/cyclone-iv/cyiv-53001.pdf)  Look at the 'Core Performance Specifications' section. This section details the maximum frequency that various devices and speed grade combinations will operate at.  Also look at the 'PLL Specifications' that immediately follows the above section. This identifies the maximum input clock frequency that the PLL can operate at for various speed grades. These figures are not the same as the those stated in the Core Performance Specifications. Both tables should help guide you as to what to expect.  However, I will say again that, the maximum clock frequency that the device will operate at will be dominated by your logic and how you've designed it. Code something, constrain it and use the tools to tell you exactly what clock frequency your design will run at. This is by far and away the best way to determine what frequency your chosen part, with your design, will operate at.  Regards, Alex

[Altera_Forum]

Hi, 

 I want to know the maximum frequency of cmos signal that the cyclone-IV will accept as its input ? I am not worried of PLL & core frequencies.  Regards, Thulasi

[Altera_Forum]

Look at the 'Periphery Performance' section of the same document. 

 "I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load."

[Altera_Forum]

Hi, 

 Thanks a lot for your reply. It helped me a lot.  Regards, Thulasi

[Altera_Forum]

Anyone has similiar statement for a Cyclone V SoC devboard? Using 5CSEMA4u23c6? I read almost everything datasheet-wise and they don't make any definite statement other then "Quartus will limit it to whatever the device is capable of". 

I think the datasheets got worse over time (I'm with Altera since Cyclone I times).

[Altera_Forum]

Cyclone IV datasheet specifies 

  --- Quote Start ---  I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load.  --- Quote End ---    I don't see a reason to expect lower speed for Cyclone V, but it's a different question if 200 MHz is feasible with the connected peripherals.