CYCLON V + DDR3 RAM reset/clock problems within BeMicro CV board

[Altera_Forum]

Hello everyone, 

I am using the BeMicro CV Development Kit board which is based on a Cyclone V Device 5CEFA2F23C8N. I am using Quartus II 64-Bit Version 13.1.0 Build 162 ( problem also occurs with Version 14.0 ) and I am hanging in 2 problems: 1) sometimes after downloading the elf file: Note: The problem occurs always   if an external PLL is used:  Verifying 08000000 ( 0%)  Verify failed between address 0x8000000 and 0x800D71F  Leaving target processor paused 2) Reset problem: the reset does not work at all even though I followed the instructions  http://www.altera.com/support/kdb/solutions/rd07072011_71.html  The board will be dead if I press the reset button. Enclosed, please find all the referece files. The myload.sh script in the flash directory will load and start the test programm to the BeMicro CV board. I have testet 5 boards already with the same result. Can anyone confirm that there is a problem in the CYCLONE V which is clock/PLL related. If yes, is there a fix available ? or did I make a mistake in my qsys design? Many thanks in advance Reinhard

[Altera_Forum]

Start with my DDR3 example ... 

 http://www.alteraforum.com/forum/showthread.php?t=43992  The reset on the Hard IP core does not work correctly    --- Quote Start ---   Service Request#11062538  Cyclone V DDR3 UniPHY HMC Avalon-MM wait-request lockup after soft-reset  The uploaded zip file contains an example design for the BeMicro-CV device. While testing the DDR3 UniPHY controller, it was determined that pulsing soft-reset caused the Avalon-MM interface to lock-up. A Modelsim simulation was created that reproduces the problem, i.e., for some reason the DDR controller forces wait-request to be asserted after the soft-reset signal has been pulsed. The simulation shows that if the global-reset signal is pulsed, the testbench works fine.  Altera's Knowledgebase article  http://www.altera.com/support/kdb/solutions/rd05212013_358.html  has the comments that   "Altera strongly recommends using only soft_reset_n at all times.  Use global_reset_n only for Power on reset."  So, what is wrong with the Cyclone V Hard-memory controller?  The file altera_service_request.txt has details on how to synthesize and simulate the design example.   --- Quote End ---   This has yet to be resolved, but the example I have referred you to works fine.  Cheers, Dave

[Altera_Forum]

Dave, thank you very much for your info but the "bemicro_cv_basic" does not realy help me. I will try to implement the fix from the Altera's Knowledgebase

[Altera_Forum]

--- Quote Start ---  Dave, thank you very much for your info but the "bemicro_cv_basic" does not realy help me. I will try to implement the fix from the Altera's Knowledgebase  --- Quote End ---    You didn't scroll down far enough in the other thread. Go all the way to the bottom and download bemicro_cv_examples.zip.  Cheers, Dave

[Altera_Forum]

I followed the instructions from you but the problem still exists. 

Enclosed, find the Qsys-file. I also figured out, that there is a CYCLON V PLL bug in the first silicon version and it is also described in the ALTERA Errata Sheet for Cyclone V Devices. http://www.altera.com/literature/es/es_cyclone_v.pdf All my BeMicro CV boards are equipped with known bad CYCLON V silicon. Too bad for me. My question: Is there a solution available and not only a Workaround ? Can I get my BeMicroCV boards replaced from ALTERA? Any Any idea is welcome. Regards, Reinhard

[Altera_Forum]

--- Quote Start ---   All my BeMicro CV boards are equipped with known bad CYCLON V silicon.   --- Quote End ---   Weird. I ordered several when they first came out from Arrow USA and they have production silicon. I wonder if the European distributors had ES parts.  You could contact the distributor and see if they'll replace them ... or give you a discount :)  Cheers, Dave