Can VREF be other than VCCIO/2?

[Altera_Forum]

Must VREF be equal to 1/2*VCCIO, or can it be, say, 2/3*VCCIO? 

 BTW, I'm using a Cyclone III M164 package. (very small physical board constraints)  I'm trying to interface to a chip that has a voltage standard just slightly different than the Alteras support. It's "this close." I am confident the design has plenty of margin for the Altera to receive the signals. But I'm not sure the Cyclone has enough margin on the transmission specs. If VREF truly operates the way it is described, then it shouldn't matter where VREF lies (well, it still has to be between VCCIO and GND of course).  Alternatively, I could RECEIVE the signal on one pin with one IO standard (HSTL-12) and transmit on another (1.2-V LVCMOS). But can I do that? And can I do it within the same IO bank, so long as the same VCCIO is acceptable with both IO standards?  I'd appreciate any and all help with this one..  thanks, ..dane

[Altera_Forum]

--- Quote Start ---  But I'm not sure the Cyclone has enough margin on the transmission specs.  --- Quote End ---   VREF is meaningless for transmission (outputs), it only affects inputs. The acceptable input voltage range of the voltage referenced I/O standards is basically the same as for differential standards, because they are using the same differential input buffer of Altera FPGAs. If you refer to LVDS common mode specification, you'll notice, that it's considerably larger than the SSTL or HSTL VREF range.  If you refer to output behaviour, you can simply assume, that all I/O standards (except for dedicated LVDS drivers) are using the same set of highside and lowside output transistors and thus achieve the same output I/V characteristic.

[Altera_Forum]

What about memory VREF? I am having issues using DDR memory. I've connected fpga memory banks to 2.5V power supply and their VREF pins to 1.25V using two 1K resistors as divider (yes, my bad, I've saved money and didn't place special DDR memory power supply driver). Now when I power up my board, the 2.5V is OK, but I see 2.0V on VREF pin instead of 1.25V. Maybe I don't need to power VREF pin at all? 

 P.S. This happens when FPGA is not configured, I didn't test it configured to use memory.  P.P.S. all other banks where memory is not connected use 3.3V. Core voltage is OK.

[Altera_Forum]

When the FPGA isn't configured, the VREF pins are disabled with a weak pull-up, as any other I/O pin. That's why you are measuring a value different than expected. Do a new measurement with the FPGA properly configured.

[Altera_Forum]

This seems to be a rather unusual problem, because regular DDR designs need a VTT driver, which can easily supply VREF as well. VREF input current in unconfigured state is meaningless, I think, but I would suggest a lower divider impedance than 500 ohm and of course effective bypassing.

[Altera_Forum]

After configuration it gets dropped to 0.8V. Memory clk is 85MHz. However, when I upload the design, the FPGA gets warm in about 20-30sec. I would say it gets hot, compared to devkit. I barely can keep finger on it.

[Altera_Forum]

Shorted outputs are the most popular reason for excessive current consumption, I would check the pinout file against the schematic in a first step. Also check all supply voltages and - if possible - determine which supply pins are sinking high current. 

 If it's your own PWB, also wiring and solder faults should be considered.

[Altera_Forum]

--- Quote Start ---  VREF is meaningless for transmission (outputs), it only affects inputs. The acceptable input voltage range of the voltage referenced I/O standards is basically the same as for differential standards, because they are using the same differential input buffer of Altera FPGAs. If you refer to LVDS common mode specification, you'll notice, that it's considerably larger than the SSTL or HSTL VREF range.  If you refer to output behaviour, you can simply assume, that all I/O standards (except for dedicated LVDS drivers) are using the same set of highside and lowside output transistors and thus achieve the same output I/V characteristic.  --- Quote End ---    I'm not sure I understand what you mean about input ranges; are you suggesting that the transition region is the same regardless of IO standard and that they give different input ranges on the datasheet just to make it look more "typical?"  As for output characteristics, I understand that the voltages will typically swing much closer to V,out,low,min and V,out,high,max assuming the output isn't too heavily loaded. But again, if the output drivers all exhibit the same characteristic regardless of IO standard, then why go to all the trouble to list the different in/out modes?  I have a sneaky suspicion I'm missing something obvious here..    --- Quote Start ---  What about memory VREF? I am having issues using DDR memory. I've connected fpga memory banks to 2.5V power supply and their VREF pins to 1.25V using two 1K resistors as divider (yes, my bad, I've saved money and didn't place special DDR memory power supply driver). Now when I power up my board, the 2.5V is OK, but I see 2.0V on VREF pin instead of 1.25V. Maybe I don't need to power VREF pin at all?  P.S. This happens when FPGA is not configured, I didn't test it configured to use memory.  P.P.S. all other banks where memory is not connected use 3.3V. Core voltage is OK.  --- Quote End ---    FWIW, 2.5V voltage divider through two 1K resistors is only 1.25mA bias current. I don't recall what kind of input currents are necessary, but you may not be giving yourself enough margin. You want the "wasteful" current through your divider network to be at least a magnitude greater than what you're using out the midpoint node of the divider network (the Vout point) so that fluctuations in the current used have a 10% or less effect on the voltage drop through the upper side resistor. You'll of course also want to make sure you have some holdup and/or decoupling caps on the output of your divider as well.    --- Quote Start ---  When the FPGA isn't configured, the VREF pins are disabled with a weak pull-up, as any other I/O pin. That's why you are measuring a value different than expected. Do a new measurement with the FPGA properly configured.  --- Quote End ---    I wouldn't think it would be changing the midpoint by 60% though if the voltage divider was properly biased?  Socrates- just a sanity check- are you sure you have two 1K resistors and not accidentally two 10K resistors?    --- Quote Start ---  Shorted outputs are the most popular reason for excessive current consumption, I would check the pinout file against the schematic in a first step. Also check all supply voltages and - if possible - determine which supply pins are sinking high current.  If it's your own PWB, also wiring and solder faults should be considered.  --- Quote End ---    +1  cheers, ..dane

[Altera_Forum]

I am sure those resistors are 1K. I've also tried 100ohms, but just to see if it changes something.  

Thats my own PCB with EP3C40. Two boards are behaving the same, so I suppose the problem could be somewhere in the schematic. I've connected all VREF pins to 1.25V and all banks where memory is connected is powered 2.5V. The FPGA gets hot only when I upload a design which use memory controller. The PLLs are fine - separately works OK and using altmemddr works fine too. Series termination: 22ohm, parallel termination 47ohm. I am not sure where else I could do a mistake.

[Altera_Forum]

@dane: The expectable real output behaviour can be reviewed from the Cyclone III Ibis files. You'll notice, that the output I/V characteristic is identical e.g. between CMOS12 and HSTL12 with same current strength.  

 You can get some ideas about structure of multi-I/O-standard form Altera patent US 7855577 " Using a single buffer for multiple I/O standards".  Of course, I'm partly guessing about undocumented features. But some conclusions are quite obvious, I think.