PLL frequency lock range

[Altera_Forum]

Hi, 

 I have a serial video signal that I want to take into an FPGA, with a parallel clock that could range from about 20MHz up to 150MHz. I'm using an Arria II GX. Am I able to get the PLL in the FPGA's transceivers to lock to an unspecified frequency within that range?  Cheers,  Alex

[Altera_Forum]

Alex, 

 The easiest way to handle this is to feed the data and clock into dual clock fifo. This allows the input data/clock to vary to any value. Then you can process with a fixed clock on the other side. No changes in the PLL input frequency.

[Altera_Forum]

Hi, 

 I need to divide the parallel clock's period in order to sample the high speed serial signal. I thought I needed a PLL for that. Is there another way, using a dual clock fifo in the design?  Cheers  Alex

[Altera_Forum]

If what you need is a division and not a multiplication, then no PLL is needed. You can use a clock enable system instead. Put your parallel clock as the FIFO write clock, and only enable the FIFO's write signals on the clock cycles that have valid data on.

[Altera_Forum]

I assume, that you an DVI-like interface. In this case, a PLL will be obviously needed. Altera PLL specification doesn't provide a wide lock range as you are requesting, although the actual lock range may be considerably larger than the spec. A frequency discrininator and PLL reconfiguration can be a solution.