Sorry it cannot be. The reason is because the absolute maximum rating for IO is 3.9V. Anything beyond that will cause damage to the I/O buffer.
With 10K pullup to +5V, add a 33K pulldown to 0V. This will cap the node to ~3.8V when not driven by the FPGA output.
The additional 33K load to ground can easily be overdriven by an output (ie, 120uA).