Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20688 Discussions

Can't access JTAG chain: Stratix III dev board

Altera_Forum
Honored Contributor II
1,477 Views

Hi,  

 

I am using a StratixIII development board EP3SL150F1152 with QuartusII 9.1 on Windows 7 and was trying to download the ".sof" example that comes with the development kit to do a preliminary setup. When I first downloaded, the board was working fine (with green LEDs supposedly flashed). That was the only download I did and the next download in afew days failed with error by the Programmer  

"Error: Can't access JTAG chain Error: Operation failed". 

 

I tried to run the JTAG chain integrity test with the error message: 

Error: JTAG chain problem detected 

Error: No device detected 

Error: The TDO connection to the download cable might be shorted to VCC or is an open circuit  

Error: The TCK and TMS connections to the last device might have problem.  

 

I also tried to remove the JTAG server, but it won't allow me with the following error "Attempted access JTAG server -- internal error code 45 occurred".  

 

I have tried several troubleshooting like changing USB cable, unset the PC firewall, re-install the Quartus version, reinstall the USB-Blaster device driver, download with another PC, use a different ".sof", check the board DIP switches and pins setup that follows the development kit user guide. But it just won't download. I reckon this could be board problem and not software version issue, but I have no idea what's gone wrong...any hints or suggestions are appreciated. Thank you.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
373 Views

Is the board still active? There should be a default configuration in the flash for the stratix that should make some leds flash when you power up the bard. 

It looks indeed like a hardware issue more than software. On the development board there is a MAX chip that does the USB blaster functionnality. It is this chip that controls the JTAG signals to the Stratix. You should that the dip switches connect the right MAX pins to the Stratix JTAG ports, and it's probably best to get the right setup from the schematic rather than the documentation because there can be some mistakes in the doc. 

Do you have an external USB blaster? If yes you could connect it to the board and check both the MAX chip and the Stratix (by putting the DIP switches in the correct positions to connect the external JTAG port to the correct chip).
0 Kudos
Altera_Forum
Honored Contributor II
373 Views

I have attached a snapshot of the board with switches positions that follows the board setup user guide when it is powered up. According to the development board setup p4-3 (SIII Development Kit User Guide), with these switch positions, the green LEDs 0-7 should flash side-to-side pattern, but in my case, it does not. This happens since downloading the sample "my_first_fpga.sof" which was the one and only successful download I did.  

 

But even with "my_first_fpga.sof" design, the LEDs should flash but it does not, which is strange. It could have been I have downloaded the wrong "sof", and so was thinking of configuring the board to factory default by pressing the FACTORY_CONFIG and RESET_CONFIG buttons before turning on the power switch, but that still does not allow me to download anything. 

 

So far, I've been using the embedded USB Blaster with the USB cable download method. Without an external USB Blaster cable at the moment (since I can't find any yet), is there a way to download without using JTAG mode? Passive serial (PS) seems to work, but it needs the external Blaster cable. Correct me if I am wrong.  

 

Any suggestions on the snapshot that does not look right? 

Thank you.
0 Kudos
Altera_Forum
Honored Contributor II
373 Views

I'm not sure of the switches orientations and I don't have a kit here to check it, but the first signal I would check is the MAX_ENABLE (4th contact on SW1). It controls the MAX_OE signal, and must be at a high level to enable the MAX II. This means that the contact must be open. If necessary check with a voltmeter that the signal is indede high. 

 

The .sof file that you uploaded was just put into the FPGA's RAM and probably hasn't changed the flash memory. Turning the power off and on again should have reloaded the default setting from the flash. If it doesn't do so it is either because of a hardware failure, or a switch configuration that prevents the MAX II from loading the correct configuration into the FPGA. 

If you are still stuck you should contact a local Altera representative to see if they can help you figure out what's wrong with the board.
0 Kudos
Reply