Can't fit fan-out of node into a single clock region

[Altera_Forum]

Hi, 

I've encounterred with this promblem.I use the ep2c20f256c8 ,design with 1 pll and 20 channels of lvds transmitter. input clock freq is 50MHz,pll output clocks' f is 200MHz,100MHz,50MHz,and it works well. but when i change the pll into: 200MHz,100MHz,25MHz, quartus give me an error "Can't fit <clk2> fan-out of node into a single clock region",where clk2 is the 25MHz output of pll This is my 1st time seeing this error,What should i do?

[Altera_Forum]

That sounds like a PLL setting error. When you were in the MegaWizard, and setting up the PLL, did you have Cyclone II selected as the device family? The PLL capabilities are different from family to family, so it may just be that for whatever reason, the combination of those clocks don't work with the Cyclone II pll. (I haven't tried). The error message is a bit confusing. I haven't seen that particular message. 

 However can easily try to use the first PLL setting and just supply a simple flop to divide it externally from the PLL.  Pete

[Altera_Forum]

--- Quote Start ---  Hi, I've encounterred with this promblem.I use the ep2c20f256c8 ,design with 1 pll and 20 channels of lvds transmitter. input clock freq is 50MHz,pll output clocks' f is 200MHz,100MHz,50MHz,and it works well. but when i change the pll into: 200MHz,100MHz,25MHz, quartus give me an error "Can't fit <clk2> fan-out of node into a single clock region",where clk2 is the 25MHz output of pll This is my 1st time seeing this error,What should i do?  --- Quote End ---    My problem was solved when I replaced two cascaded PLLs with a single PLL (in cyclone II).