Consider the following code:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
always@(posedge clock or negedge reset) begin
if(!reset) data <= 1'b1;
else if(clk_enable)
data <= ~data;
end
It creates the following circuit
and this is my target design. Now consider the following layout:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
clkena_test clkena_test(
.clock(*****????*****),
.reset(reset),
.data(data)
);
with module clkena_test containing
module clkena_test (
input wire clock,
input wire reset,
output reg data = 1'b1
);
always@(posedge clock or negedge reset) begin
if(!reset) data <= 1'b1;
else data <= ~data;
end
endmodule
You can see that module clkena_test does not use clock enable.
Is there any way to tell Quartus to create clock enable signal within any clock use in clkena_test module? The workaround could be opening clkena_test.v file, and manually add if(clkena) into every always construct. But this would not work if I use auto-generated IP which may be overwritten by the tool, and thus all changes will get lost. Note: gated clock is NOT a solution.
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Thank you very much! I have several questions left:
1. how many clock controllers can be set up in Cyclone 3? They seem using dedicated logic, but I can not find this information in the documentation;
2. should I pass both master clock, and slower clock through clock controllers for compensate for the delays in them? (see below)
