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Altera_Forum
Honored Contributor I
800 Views

Configuration and initialization of HPS - I/O in Cyclone V

Hello, 

I’m working on a bare-metal application with Altera Cyclone V with assembly language. 

I need to configure the I/O bank properties before use the pin by the peripherals in HPS. 

I read that this configuration is made in the Scan Manager by configuring the Scan Chains. 

For that I have to write configuration words in the FIFO registers. 

I cannot find data describing the words to write in the FIFO according to the I/O configuration. 

Where can I find these information?  

Where can I find these examples?  

Thanks for your help 

Jerome 

Hello,
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4 Replies
Altera_Forum
Honored Contributor I
37 Views

No, this is configured for the IP in Platform Designer (Qsys), which generates the .sopcinfo file used to created the preloader (second stage bootloader). This is much easier and is the recommended flow.

Altera_Forum
Honored Contributor I
37 Views

Bonjour, 

Merci beaucoup pour votre réponse que m'aide à mieux comprendre la partie FPGA. 

Ma question concerne plus de la partie HPS au début de flux de développement. 

 

Le DS-5 AE ne peut pas avoir accès à HPS GPIO qui est indisponible. 

Je sais qu'il est nécessaire de d'abord initialiser des registres(enregistreurs) pour rendre le HPS GPIO accessible. 

Par exemple il est nécessaire de remettre le morceau(bit) 26 (GPIO1) du registre(de l'enregistreur) permodrst du directeur(manager) remis pour sortir l'état remis de GPIO1. Mais cette action ne suffit pas et je dois savoir(connaître) ce qu'il est nécessaire de faire. 

Merci de votre aide.
Altera_Forum
Honored Contributor I
37 Views

Excuse me for the French reply posted by error 

 

Hello, 

Thanks very much for your reply which help me to better understand FPGA part. 

My question concerns more the HPS part at the beginning of development flow. 

 

The DS-5 AE cannot access to HPS GPIO which are unavailable. 

I know that it is necessary to first initialize registers to make the HPS GPIO accessible. 

For example it’s necessary to reset the bit 26 (GPIO1) of the register permodrst of the reset manager to release the reset state of GPIO1. But this action is not sufficing and I need to know what it’s necessary to do. 

Thanks for your help.
Altera_Forum
Honored Contributor I
37 Views

As I said, the second stage bootloader should be doing this for you when you do "Run as hardware" in DS-5. Did you build the second stage bootloader?

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