I have a design where the FPGA receives clk and data (DDR) . The timing spec of the sender respect to the clk edge is fixed at all frequencies.
The sender can configure the frequency of the DDR interface. The DDR clk goes to a PLL in the FPGA. The clkout is the same frequency as clkin but shifted. The bandwidth of the PLL is setup to lock with the maximum and minimum frequency of the sender DDR clk. There could be many combination of frequencies depending what clock source is used for the input of the divider in the sender device.
My question for the timing constrains, can I used the worst case frequency only?
note: The PLL must be compiled with the minimum frequency of the inclk (parameters were manually modified using an Altera AN to expand bandwidth)
If I do this , at compile time I get a warning
Clock: 2A|altpll_component|auto_generated|pll1|clk[0] with master clock period: 10.000 found on PLL node:2A|altpll_component|auto_generated|pll1|clk[0] does not match the master clock period requirement: 12.50
this message is because my virtual clk period is set to the max freq. (The PLL inclk is set for min)
If I use multiple frequencies with the -add_delay , I can't possible cover all combinations.
thanks
