Critical Warning: Timing requirements not met

[Altera_Forum]

Hi everybody, 

 When i compile my design on Quartus II, it gives me the following errors:  "Critical Warning: Timing requirements are not met."  "Critical Warning: Found minimum pulse width or period violations. See Report Minimum pulse width for more information."  "Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning: From clk (Rise) to clk (Rise) (setup and hold)"  Can anyone explains to me what is happening

[Altera_Forum]

Add "derive_clock_uncertainty" to your .sdc. (In newer versions of Quartus this command runs automatically, but you still get a warning.) 

You have failing paths in your design. Launch TimeQuest, run the macro on the left side called Report All Summaries. Find the red, right-click and do a Report Timing on the failing paths.  (Note that Report Minimum Pulse Width failures stem from "datasheet" numbers. For example, a memory might be spec'd to run at 400MHz, and if you drive it with a clock at 425MHz, you get this failure. It's not so much static timing analysis of individual components, but specs on how fast something can run. Common ones are memory blocks, I/Os, clock trees and dynamic reconfiguration ports(such as PLL/Transceiver reconfiguration).

[Altera_Forum]

Thank you very much. When I defined the clock by the create_clock and derive_clock_uncertainty commands, the warnings gone.