Custom board on Cyclone V SoC HPS SDRAM topology unclear

[BrianSune_Froum]

Dear Intel and All,

This is Brian, I am working on a C5 SoC project.
According to document "emi_plan-683385-666390.pdf"

"Leveling circuitry is dedicated I/O circuitry to provide calibration support for fly-by
address and command networks. For DDR3, leveling is always invoked, whether the
interface targets a DIMM or a single component. For DDR3 implementations at higher
frequencies, a fly-by topology is recommended for optimal performance. For DDR2,
leveling circuitry is invoked automatically for frequencies above 240 MHz; no leveling
is used for frequencies below 240 MHz.
For DDR2 at frequencies below 240 MHz, you should use a tree-style layout. For
frequencies above 240 MHz, you can choose either a leveled or balanced-T or Y
topology, as the leveled PHY calibrates to either implementation. Regardless of
protocol, for devices without a levelling block—such as Arria II GZ, Arria V, and
Cyclone V—a balanced-T PCB topology for address/command/clock must be used
because fly-by topology is not supported.
For details about leveling delay chains, consult"

This is making me very puzzling about do DDR3 Fly-by is allowed or not?

[sstrell]

It's been a while since I've used DDR3, but fly-by is certainly allowed.  You specify in the IP Parameter Editor that the memory is organized in such a topology and that enables the automatic leveling based on when signals reach each chip.  It's recommended for most implementations but required at 400 MHz and above.

[BrianSune_Froum]

Maybe allow me to rephase or explain a bit more what i am trying to ask or confirm.

What i am seeking is a confirmation on HPS hard memory controller that is allow user to design in fly-by topology.
I am not asking about the external memory controller in PL side.

If this is align with what you had mentioned please do confirm or provide documents I am willing to read more.

Thank you

[sstrell]

TBH, it's not clear: https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/sdram-controller-subsystem-40997.html

I know the hard memory controller in the CV fabric does support fly-by.  It is not mentioned in this HPS documentation.

The easiest thing to do would be to simply create an HPS instance in Platform Designer and see if the option is there in the component's parameter editor.

[BrianSune_Froum]

I am afraid there are still no information to confirm such.
Meanwhile, there are still more puzzling factors.

If possible do you have any idea that Altera do have open example layout from the beginning for engineer to reference?

Appreciated

[AdzimZM_Intel]

Hi Brian,

Leveling is not supported for Cyclone V device.

Please refer to this link in Note 10: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/uniphy-based-external-memory-interface.html

For reference material, you may refer to to Cyclone V SoC devkit.

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-sx.html

Regards,

Adzim

[BrianSune_Froum]

@AdzimZM_Intel 

Please do confirm the below understanding is aligned.

" 13. For Arria V, Arria V GZ, Cyclone V, and Stratix V."

So simply said HPS hard EMI also this rules?

" 10. & 13."
So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?

"10. Leveling is not available for Arria V or Cyclone V devices."
DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? 

Thank you

[AdzimZM_Intel · Accepted solution]

Hi Brian,

"So simply said HPS hard EMI also this rules?"

• Yes the HPS EMIF IP also same.

"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"

• Yes, it's not supporting DDR3 SDRAM fly-by topology

"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "

• Yes

Regards,

Adzim

[BrianSune_Froum]

@AdzimZM_Intel 

I am afraid during testing and referencing to Altera inherent design files.

I am so confused and puzzled why leveling is not allowed but such routing is allowed?

According to T-Branch layout it is almost defined it must be even # of dies.

But if the middle join is the ECC it is still understandable but in this route and design it is a fly-by just first node termination.

This violated all the discussion previously?

Please do explain.

[BrianSune_Froum]

The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
The MT41K128M16  /w 1k page size shows no sanity issue on memtest stresapptest on distro.
UBOOT memory normal test also passed w/o any errors.

So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

No matter it is /w or /wo the board settings no drop no crash no stuck.

So the case ends here.