Cyclone V GX starter Kit : XCVR_LOOPBACK_TEST clocking from REFCLK_p0 to PLL Reconfig inside xcvr ip

[jkhoo]

Hi Intel team,

In the C5G_HSMC_XCVR_LOOPBACK_TEST project,

1. clock generator si5338 CLK1A (U20.Pin18) with default frequency of 125Mhz is connected to REFCLK_p0. 
2. And REFCLK_p0 is routed to hsmc_xcvr_clk_clk port in the c5g_xcvr_qsys u0 instance.
3. the clock source (hsmc_xcvr_clk) in c5g_xcvr_qsys.qsys is set at 100Mhz.
4. since c5g_xcvr_qsys.qsys is constructed of four C5_HSMC_XCVR.qsys IP. i notice the clock source (ref_clk) in C5_HSMC_XCVR.qsys is set to 644.53Mhz.
5. I also notice the PLL Reconfiguration in xcvr_custom_phy_0 is set to 100Mhz.

So my question is, why is the PLL reconfiguration reference clock freq set to 100Mhz when the project top entity is getting default freq of 125Mz from si5338. 

And why is the ref_clk in C5_HSMC_XCVR.qsys set to 644.53Mhz when PLL reconfiguration reference clock freq set to 100Mhz.

[ZiYing_Intel]

Hi jkhoo,

Can you share your .qar file?

Best regards,

Zi Ying

[jkhoo]

Hi Zi Ying,

Here are the qar file attached.

JJ

[ZiYing_Intel]

Hi JJ,

Are you using Quartus Pro 22.2 in this case?

Best regards,

Zi Ying

[jkhoo]

I am using Quartus Prime Standard edition 18.1

[ZiYing_Intel]

Hi,

Currently there is no a probable reason that why is the PLL reconfiguration reference clock freq set to 100Mhz when the project top entity is getting default freq of 125Mz from si5338 because it might be caused by many factors.

Best regards,

Zi Ying

[jkhoo]

Hi Zi Ying,

Can it concluded that :-

• the ref_clk in C5_HSMC_XCVR.qsys is wrongly set to 644.53Mhz and
• PLL reconfiguration reference clock freq is wrongly set to 100Mhz.

And i should set them to 125Mhz.

Regards, JJ