Cyclone V HPS DRAM Size (defined in Quartus, QSYS)

[Altera_Forum]

I'm looking into how the DRAM is setup for Cyclone V in Quartus/QSYS. I can change the HPS DRAM parameters (shown in attached photo) for row address, column address, bank address which reflect the datasheet. My question within Quartus / QSYS is there other places I need to look to setup the proper DRAM size? I can generate uboot/preloader and the right DRAM size shows up on boot-up but that value is automatically calculated by uboot/preloader software. My concern is that the FPGA is setup correctly with regard to shared memory and where to check in Quartus / QSYS. 

 Thanks,