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DDR3 SDRAM Hard memory controller writing with burst length of 1

Honored Contributor II



Currently, I want to store video data by storing the pixel data in the arbitrary memory address then read it back and output to the display device (monitor through HDMI interface). The reading interface from SDRAM used burst length of 32bytes.  

If I increase the writing address continuously (by code not automatically) then I get a good image color on the monitor.  

The problem is instead of increase address one by one, I input the address with the arbitrary address that I calculated (example I want to rotate the image 90 degree) then on the monitor I get the image with losing some colors. (as you can see in the image).  

I doubt that when I change address frequently in every clock cycle then the HMC can change the address of memory row fast enough to write the data to the SDRAM. There is some delay so when the HMC can do the writing then the pixel data is starting to update with the new data, that leads to losing some bit information in the pixel data. 


could anyone give me some solution to fix the issue? 


I'm using Cyclone V 5CEFA9F31I7 and MT41J128M16 2Gb DDRR3 SDRAM. The interface to communicate with HMC I referred the ddr3 example code when generating the HMC IP in Quartus16.1
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