DE2_TV problem

[Altera_Forum]

In the file of itu_r656_decoder ,what's the affection of " if ((h< 51) || (h > 771)) " and " if ((h< 41) || (h > 781)) "? 

And " Vde_counter >31 and Vde_counter <511",why must the Vde_counter larger than 31 ?   `define sync 8'd101 module itu_r656_decoder  (  input CLOCK,  input [7:0]TD_D,  input TD_HS,  input TD_VS,  input SW0,   input SW1,   output [7:0]Y,  output [7:0]Cb,  output [7:0]Cr,  output reg HSx2,  output VSx1,  output reg Ypix_clock,   output blank );    assign VSx1=TD_VS; /////// FF 00 00 SAV(EAV) //////   reg[7:0]R1,R2,R3;  reg[7:0]RR1,RR2,RR3;  wire Y_check=( (R3==8'hff) && (R2==8'h00) && (R1==8'h00) )?1:0;   always @(posedge CLOCK) begin  RR1=TD_D;  RR2=R1;  RR3=R2;  end   always @(negedge CLOCK) begin  R1=RR1;  R2=RR2;  R3=RR3;  end /////decode SAV(EAV) ////  reg START,Field;   always @(posedge CLOCK) begin  if (Y_check==1)  begin  START=~TD_D[4];  Field= TD_D[6];  end   end //////YUV4:2:2 to YUV4:4:4/////  reg [7:0]YY;  reg [7:0]CCb,Cbb;  reg [7:0]CCr,Crr;  reg [1:0]COUNTER;   always @(posedge CLOCK) begin  if (!START)   COUNTER=0;  else COUNTER=COUNTER+1;  end   always @(posedge CLOCK) begin  case (COUNTER)  0:begin Cbb=TD_D; Ypix_clock =0;end  1:begin YY =TD_D;CCr=Crr;CCb=Cbb; Ypix_clock =1;end  2:begin Crr=TD_D; Ypix_clock =0;end  3:begin YY =TD_D;CCr=Crr;CCb=Cbb; Ypix_clock =1;end   endcase   end  ///// auto-counting H length ////  reg [10:0]H_COUNTER;  reg [10:0]RH_COUNTER;  always @(posedge CLOCK) begin  if (TD_HS) H_COUNTER=0;   else H_COUNTER=H_COUNTER+1;  end   always @(posedge TD_HS) begin  RH_COUNTER=H_COUNTER;  end  /////to generate HSx2////  always @(posedge CLOCK) begin  if (  ((H_COUNTER >= 0) && (H_COUNTER < `sync)) ||   ((H_COUNTER >= RH_COUNTER[10:1]) && (H_COUNTER < (RH_COUNTER[10:1]+`sync+1)))  )   HSx2=0;  else  HSx2=1;  end  /////H blank for HSx2/////  reg [10:0]h;  reg h_tr;  reg h_tr_h;   always @(posedge CLOCK) begin  if(!HSx2) h=0;  else  h=h+1;  end  always @(posedge CLOCK) begin  if ((h< 51) || (h > 771))   h_tr=0;  else  h_tr=1;  end  always @(posedge CLOCK) begin  if ((h< 41) || (h > 781))   h_tr_h=0;  else  h_tr_h=1;  end /////V blank for HSx2//////  reg[10:0]Vde_counter;  always@(posedge HSx2)begin  if (TD_VS==0)  Vde_counter=0;  else  Vde_counter=Vde_counter+1;  end ///v-h blank output//   wire vde=((Vde_counter > 31) && (Vde_counter < 511)) ? 1:0;//480  wire blank_h = h_tr & vde; ///vga blank output//   assign blank = h_tr_h & vde; /////dual port RAM////  wire [7:0]Yw;  wire [7:0]Cwr;  wire [7:0]Cwb;  dul_port_c1024 YYYR(  .iDATA(YY[7:0]),  .iHSYNC(TD_HS),  .iHSYNCx2(blank),  .Y_CLOCK(Ypix_clock),  .Y_CLOCKx2(CLOCK),  .oDATA(Yw[7:0]),  .field(Field),  .VS(TD_VS)   );  dul_port_c1024 CBB(  .iDATA(CCb[7:0]),  .iHSYNC(TD_HS),  .iHSYNCx2(blank),  .Y_CLOCK(Ypix_clock),  .Y_CLOCKx2(CLOCK),  .oDATA(Cwb[7:0]),  .field(Field),  .VS(TD_VS)   );  dul_port_c1024 CRR(  .iDATA(CCr[7:0]),  .iHSYNC(TD_HS),  .iHSYNCx2(blank),  .Y_CLOCK(Ypix_clock),  .Y_CLOCKx2(CLOCK),  .oDATA(Cwr[7:0]),  .field(Field),  .VS(TD_VS)   );   /////YUV 4:4:4 output////   assign Y = (blank_h)?Yw :8'h10;  assign Cr = (blank_h)?Cwr :8'h80;  assign Cb = (blank_h)?Cwb :8'h80; endmodule

[Altera_Forum]

i also don't understand these. Who can help us ?:-P