Design help options for issue...

[Altera_Forum]

Hi. I have hit a wall with my design, and i'm weighing my next move, and am wondering if a design consultant is an option. My design issue is incredibly simple, but i am not in a university setting, and I have been sorting this issue for a couple weeks now, and time to product is a factor. I need NIOS2 drivers for I2S (digital audio codec). ' Poll AD/read AD if ready/Write to DA/repeat '. (Real time DSP using delta-sigmoid AD/DA.) 

Is this something a design consultant can help me with? Too simple to request a quote? How about someone at Altera support? Thanks.

[Altera_Forum]

Do you mean I square C? If so, I think the university program has HAL driver for an I2C component.

[Altera_Forum]

--- Quote Start ---  Do you mean I square C? If so, I think the university program has HAL driver for an I2C component.  --- Quote End ---    Hi, benc. I2S is an audio serial bus protocol. I don't think it's much different than I2C or SPI in terms of complexity or implementation, but each has its eccentricities. A codec uses I2S for clock and timing, and I2C for controlling it. I've been up and down the references and examples - if there's something there i missed it. If I had an example for a 'codec In/Out loop Back' i might be all set.   http://www.interfacebus.com/i2s_interface_bus.html

[Altera_Forum]

I'm wondering if I should be looking in the University program for this function. I see there are references to an IP that looks hopeful called ' altera_audio ' - https://www.altera.com/support/training/university/materials-ip-cores.html 

Is this what i need? I see there is an IP called 'audio' in the IP library in Queartus Prime Lite - is this the IP i should probably be looking at?  Also, could this be the IP core I am looking for? I would need to adapt it to work on my Intel Max10 Development kit or Terasic Max10 NEEK boards - is this possible? Thanks for any help. file:///ip/altera/university_program/audio_video/altera_up_avalon_audio/doc/Audio.pdf   https://alteraforum.com/forum/attachment.php?attachmentid=15676&stc=1

[Altera_Forum]

I see. So it is different from I2C protocol. 

 A quick check on the Altera site yields the following: https://www.altera.com/solutions/partners/partner-profile/system-level-solutions--inc-/ip/i2s-controller.html#getting-started An I2S controller from System Level Solutions, Inc.  It supports open core plus, so I guess you can request an evaluation copy of the IP from them.

[Altera_Forum]

That looks very helpful, benc, thanks.  

 I just ran across a project and code that i hope is all i need in NIOS2 for loop-back template. Just few lines of C - it's from years ago, so i am wondering if it needs to be modified, and by how much...  http://www.diva-portal.org/smash/get/diva2:22246/fulltext01.pdf (NIOS code below) by José Ignacio Mateos Albiach 2006.  I am not sure yet if i should expect to be able to use this same NIOS code on Max10 Dev. boards., NIOS2 Qurtus II, or Quartus Prime. But it IS a simple example to get started from, and perhaps now i can spot similar code in the demos and examples for Intel and NEEK boards, and isolate these functions.   Here's the 'loop back' code from the linked DE2 project:   <stdio.h>  # include "system.h"  # include "altera_avalon_pio_regs.h"  # include "alt_types.h"   int main() {    alt_u32 data;   int ready;   int rdy;    data=0;   rdy=1;    while(1) {   ready = IORD_ALTERA_AVALON_PIO_DATA(READY_BASE);   if (ready==1)   {   rdy=1;   }    if ((ready==0) & (rdy==1))   {   rdy=0;   data = IORD_ALTERA_AVALON_PIO_DATA(DATA_FOR_NIOSII_BASE);   IOWR_ALTERA_AVALON_PIO_DATA(DACDAT_BASE, data);   }     } return 0;  }  I don't know if i can use the same functions as shown, but for Max10 NEEK board or Intel Max10 board yet, or something entirely different, but it may help. The project builds the IP it needs by the looks of it. No audio 'includes', no Quatrus library 'audio' IP cores.

[Altera_Forum]

It looks like this project uses a PIO component in SOPC builder for NIOS II to communicate to a module this author wrote specifically for the audio codec he uses. I did not check if this audio codec uses the I2S protocol. If so, I guess you can reuse his code; and of course performance cannot be guaranteed (NIOS II accessing hardware modules through PIO is typically slow).

[Altera_Forum]

--- Quote Start ---  It looks like this project uses a PIO component in SOPC builder for NIOS II to communicate to a module this author wrote specifically for the audio codec he uses. I did not check if this audio codec uses the I2S protocol. If so, I guess you can reuse his code; and of course performance cannot be guaranteed (NIOS II accessing hardware modules through PIO is typically slow).  --- Quote End ---    Thanks, benc. That makes sense. I have gathered a few things since last posting, and new examples, Terasic suggests i can take parts from two demo examples to achieve this, extracting what i need from the designs. They are advanced designs +often have custom IP. Great way to learn though and i'm looking forward to mastering the most complex examples.   So as of today it looks like i need to find about four lines of code to implement in main.c, and two IP cores to configure - one for SPI data and one for I2C control registers. Please let me know if i'm on the wrong track.. :cool: Pointers, comments and suggestions welcome.   Thanks,

[Altera_Forum]

I am not sure where the "four lines of code" come from; and I am not sure about how you would "merge" the SPI and I2C IP into an I2S controller, if that is what you mean.

[Altera_Forum]

Thank, benc. I have a better picture of the system now. I see there is usually an IP block in most examples called audio to take care of I2S clocking specifically.  

 But here's a new question - i've searched Intel AUDIO CORES in the documents, and have only found one with the term AUDIO in it, but the function is to imbed audio into video. Is there an AUDIO CORE and i just missed it? Thanks,   Here is an example using an 'AUDIO' core. It's not clear if this is a Altera Intel or not.  http://www-ug.eecg.toronto.edu/msl/nios_devices/dev_audio.html    (http://www-ug.eecg.toronto.edu/msl/nios_devices/dev_audio.html) The NIOS code just needs to poll codec, write, read, reset ready flag, so i am just guessing roughly four lines in the main.c 'while' loop.  I found these lines in terasic examples - to go with their AUDIO block in Platform Designer - these in AUDIO.c -   Write: void AUDIO_DacFifoSetData(short ch_left, short ch_right){  AUDIO_DAC_WRITE_L(ch_left);  AUDIO_DAC_WRITE_R(ch_right); }  Read: void AUDIO_AdcFifoGetData(short *pch_left, short *pch_right){  *pch_left = AUDIO_ADC_READ_L();  *pch_right = AUDIO_ADC_READ_R(); }  ..and these in Man.c -    AUDIO_AdcFifoGetData(&ch_left, &ch_right);  data = (ch_left << 16) | ch_right;  *pRecording++ = data;     ch_left = data >> 16;  ch_right = data & 0xFFFF;  AUDIO_DacFifoSetData(ch_left, ch_right);    These are in with many other lines, but i am hoping these are the crucial lines i need for basic read/write via NIOS, does this look likely? Thanks,