Hi I'm developing my own FPGA board using a Cyclone IV E EP4CE10E22C8N but when I use the USB blaster JTAG, it says it cannot scan the device chain. I have measured the configuration pin voltages (nSTATUS, nCONFIG, and CONFIG_DONE) and have found them to be 0V, 1.2V and 0V respectively. The hardware one each pin is a single series pull up resistor of 4k7 ohms to a 2.5V supply for each pin. Below is an excerpt from my schematic with measured voltages in red.
From "Figure 1: Configuration Cycle Waveform" on this Intel document (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf51001.pdf) I suspect I am stuck somewhere in the reset or early configuration section. Why this is I do not know.
I am puzzled why I see 1.2V on the nCONFIG pin, surely this ought to be either 0V or 2.5V?
One thing I feel might play a part is that these pins are pulled up to 2.5V, not the 3.3V I am using on my VCCIOx pins. This Intel document (https://www.intel.com/content/dam/altera-www/global/en_US/others/download/board-layout-test/schematic-review-ws/worksheets/Cyclone_IV_Schematic_Review_Worksheet.doc) on pgae 19 states that nCONFIG should be connected to VCCA (I believe 2.5V in this case) if a PS configuration scheme with a download cable is being used. However I am unsure what a PS configuration scheme and download cable specifically are.
The same section states that nCONFIG should otherwise be connected to VCCIO (in my case 3.3V NOT 2.5V). Is this where I am going wrong? Before I alter my PCB I would like to check that this modification will not damage my FPGA or USB Blaster. Here is a larger section of my FPGA power and configuration portion.
Thanks in advance for your help.
Link Copied
Hi Anand,
Many thanks for your detailed response, I really appreciate the effort. In answer to each of your points:
1) I measured the 4 voltages of interest (5V main supply, 3.3V for IO, 2.5V and 1.2V) during switch on. The waveforms are as follows:
Where c1 = 5V, c2 = 3.3V, c3 = 2.5V and c4 = 1.2V. The verticle scale is constant at 1V/div and the horizontal scale is also constant at 1ms/div. From the point the 5V supply turns on it takes only 1.2ms for the three FPGA supplies to start. From this point in time, the three supplies reach their rated voltages in just less than 2ms. From the Cyclone IV Device Datasheet (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf) page 1-5 states that:
"(5) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms.
(6) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within 3 ms. "
I don't know if I'm configured for standard or fast POR, but evidently the <2ms POR meets both criteria.
2) The can't scan JTAG chain message appears when I attempt to use the "Auto Detect" button in the Programmer in Quartus Prime Lite Edition. I am not doing any other configuration steps before this - should I be?
3) This is a custom board.
4) I've checked the JTAG pins and am fairly sure they are correct. I've also checked to ensure there are no open connections or shorts here.
5) I believe the connection between Blaster and JTAG header is ok.
I am quite puzzled by the 1.2V state on the nCONFIG pin. As it is pulled up to 2.5V, surely it should be at either 0V or 2.5V in a normal logic state? Or is there additional behaviour? I have included my schematic as a pdf for your consideration. The main FPGA is presented on page 3. The JTAG header is on page 6, labelled as CON 11. My possible concern is that my supply voltages are not correct (including on JTAG) . What do you make of them? Below is a drawing of my JTAG connector (CON 11) as if you are looking into it. The notch is indicated for the Blaster connection.
Thanks again in advance.
Hi Tbake8,
There are a few things that I think could be of issue. There has been a good back and forth between you and Anand, so forgive me for lack of continuity.
First, lets address your confusion about passive serial configuration. The FPGA can configure itself/be configured in a variety of ways. See chapter 8 of the Cyclone IV handbook to read about the differences between active configuration vs. passive configuration vs. JTAG configuration.
To not overcomplicate things, the way your FPGA is expecting to be configured is based on the MSEL pins. Based on your schematic your MSEL[2:0] pins are 010. This correlates to an active serial configuration method for your Cyclone IV device. See the below image, but your FPGA is expecting an active serial configuration scheme in the standard POR delay mode.
As to why you are seeing the strange voltage values on nCONFIG, I unfortunately cannot say right now.
But if you refer to the bottom of that image I posted, I circled another statement. What that statement is saying is: JTAG configuration should always work with this device, regardless of what your MSEL pins are. So that begs the question: “well why does JTAG config not work for me? When I try and “target” my device over the Quartus programmer, I can’t see the device.”
This is a good question, but I also am not sure at the current moment (☹). It looks like the pinout of your JTAG header (which is where the USB blaster plugs into) is correctly pinned out, but that is worth double checking. I think tackling and figuring out why you cant see your device over JTAG should be first priority. Then figuring out what is wrong with the nCONFIG, nSTATUS, and other related pins.
Also, be sure that Quartus Lite was correctly installed on your machine and that your drivers are up to date/correct.
Hope this was somewhat helpful.
