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Do any Intel FPGAs that set undefined values ​​in registers after power up exist?

flammmable
Beginner
926 Views

There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up.
- The most reliable method is using a supervisor IC which guaranteed send the reset signal. But this method needs a descrete IC on the board. Many boards haven't such supervisor.
- Less reliable method is usind a PLL lock signal for reset. But some small FPGAs (CPLDs) have not a PLL. The other counter argument is that if a PLL will fail for some clocks it cause not only skipping these clocks but the whole reinitializing of the FPGAs design.
- The other method is using some register with known default value to detect power-up condition and then changing this value. But if the registers default values are undefined this method did't work.

Do any Intel FPGAs that set undefined values ​​in registers after power up exist?

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ak6dn
Valued Contributor III
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Ok, so attached here are a couple of pages from an Altera Quartus manual that describe in detail this topic about registers.

 

Quoting:

   "Registers in the device core always power up to a low (0) logic level on all Altera devices."

 

And a coding example of setting power up default value for a register:

Example 12-38: Verilog Register with High Power-Up Value

  reg q = 1’b1; //q has a default value of ‘1’
  always @ (posedge clk)
    begin
    q <= d;
    end

Example 12-39: VHDL Register with High Power-Up Level

  SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
  PROCESS (clk, reset)
  BEGIN
    IF (rising_edge(clk)) THEN
      q <= d;
    END IF;
  END PROCESS;

 

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7 Replies
sstrell
Honored Contributor III
903 Views

When you say "undefined values", do you mean random values?  What do you want to see at power up?

For all devices, registers power up low.  However, Hyperflex devices (Stratix 10 and Agilex currently) support programmable initial conditions.  The hyper-registers in these devices can be initialized to 0 or 1 on powerup.  Is that what you are looking for?

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flammmable
Beginner
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When you say "undefined values", do you mean random values?

Yes I mean this. I want to know is there any document (or other proof) which guarantee that all registers in Intel FPGAs are low after power-up?

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ak6dn
Valued Contributor III
880 Views

When you say 'low after powerup', do you mean before or after configuration to an image has occurred?

If before, it is kind of moot, since without a program in the FPGA you can't see any register contents anyway.

After configuration, the initial value in a register will depend on the programmed image.

 

For example, I can write:

reg a = 1;
reg b = 0;

in my verilog code, and after configuration register A will have the value '1' and register 'B' will have the value '0';

There need not be any clocking or reset pulses applied. The configuration process will ensure the value is set as specified.

By default a value of '0' will be set if not specified.

 

Memory blocks are about the only logic function I have seen that may have more or less random values after power on. I have never investigated what an Altera FPGA M9K memory is set as by default. I know you can initialize it to a known set of values as part of the configuration (ie, like as a ROM) but I have never relied on it being something at powerup that i did not put in it (ie, write first, read later).

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flammmable
Beginner
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For example, I can write:
reg a = 1;
reg b = 0;

in my verilog code, and after configuration register A will have the value '1' and register 'B' will have the value '0';

<...> The configuration process will ensure the value is set as specified.


Is there any document which guarantee such behaviour for Intel FPGAs? Is there any document which guarantee that this syntax is supported by Intels syntesizer for all Intel FPGAs?

 

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ak6dn
Valued Contributor III
860 Views

Ok, so attached here are a couple of pages from an Altera Quartus manual that describe in detail this topic about registers.

 

Quoting:

   "Registers in the device core always power up to a low (0) logic level on all Altera devices."

 

And a coding example of setting power up default value for a register:

Example 12-38: Verilog Register with High Power-Up Value

  reg q = 1’b1; //q has a default value of ‘1’
  always @ (posedge clk)
    begin
    q <= d;
    end

Example 12-39: VHDL Register with High Power-Up Level

  SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
  PROCESS (clk, reset)
  BEGIN
    IF (rising_edge(clk)) THEN
      q <= d;
    END IF;
  END PROCESS;

 

Farabi
Employee
845 Views

Hello,


What device are you using now?


regards,

Farabi


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Fakhrul
Employee
817 Views

Hi flammmable,


We do not receive any response from you since the previous reply by ak6dn that has been marked as a solution.


This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.


Thank You.


Regards,

Fakhrul




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