Does CURRENT_STRENGTH_NEW limit current?

[BrendenB]

Is the output current from a pin limited when CURRENT_STRENGTH_NEW is set? For example, if I set CURRENT_STRENGTH_NEW to 10mA will the pin only allow 10mA out? If not, is there any pin setting that might be used to limit the current sourced/sunk at a pin?

I always thought that setting CURRENT_STRENGTH_NEW was just telling the FPGA to configure the pin so that the voltages required by the IO_STANDARD can be generated while the current sourced/sunk is less or equal to CURRENT_STRENGTH_NEW. It would still be possible to source/sink more than CURRENT_STRENGTH_NEW of current, but at that time the voltages may start violating the IO_STANDARD levels (or cause smoke).

The reason I ask is that the "HSMC Debug Header" from terrasic has LEDs connected directly between *two* FPGA pins without a resistor in series (there is actually a 0Ω resister but I assume it does nothing). I assumed that when the LED was turned on (by setting one pin to 1'b0 and one to 1'b1) that massive current would be generated and smoke would follow. I'm not sure what happens but I am assuming it works. Just trying to work out why. The DE10-Standard board that I am using routes FPGA pins directly to the HMSC connector (i.e. no resistors).

[AqidAyman_Intel]

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[AqidAyman_Intel]

Hi,

CURRENT_STRENGTH_NEW is a current strength logic option where it is a logic option that sets the drive strength of a pin. Specific numerical strength settings are appropriate only for pins with certain I/O standards. Specify a number (in mA), MIN, or MAX for output or bidirectional pins that support programmable drive strength. This option must be assigned to an output or bidirectional pin or it is ignored.

[FvM · Accepted solution]

Hi,
current strength specification has nothing to do with limiting output current to a certain value. The mA value defines the maximum load current that keeps output voltage drop within the logic level specification of a certain IO standard. Maximal output current, e.g. into shorted output is much higher and exceeds in most cases FPGA maximum rating so that the output driver may be damaged.

See for example the output characteristic of Cyclone 10 LP CMOS 3V IO standard with 4 mA current strength according to IBIS files.

The only IO standard that limits output current to a safe value is LVDS 2.5 V. HSMC breakout adapter is obviously designed to use this standard.

[AqidAyman_Intel]

He Brenden,

I wish to follow up with you, do you have any more concerns or questions on this issue?

Regards,

Aqid

[BrendenB]

Nope. Marked the solution.

[AqidAyman_Intel]

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