EPCQ-L NVCR Documentation is incorrect

[LD]

Concern : Intel Premier Support Case 00351159 - EPCQ-L NVCR Documentation is incorrect

Hi,

It seems that the documentation of the EPCQ-L is not correct (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf52013.pdf)

Page 19, Table 23. The bit[4] is said to be "Don't care" with a default value of '1'.

If this value is set in the NVCR register of the EPCQ, the Arria 10 does not boot anymore...

Moreover, the Quartus Programmer set the value 0xAFEE in the NVCR when programming a JIC file. (so this bit is set to 0)

If we look at the MT25Q datasheet, we see that this bit is used for setting the reset location on the pin DQ3....

Could you confirm that?

Kind regards,

Lionel

[Nooraini_Y_Intel]

​Hi LD,

Yes, you are correct. In the EPCQL device, the NVCR bit[4] is defaulted to 1. The Quartus Prime programmer and active serial configuration don't use RESET or HOLD function, thus the bit[4] is set to 0. Users are recommend to set this bit[4] to 0 to disable RESET or HOLD function on DQ3 pin.

Regards,

Nooraini

[LD]

Hi Nooraini ,

Thanks for the confirmation!

So, the documentation should be updated accordingly.

Regards,

Lionel