Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21598 Discussions

Error (12002): Port "sdr_clk_clk" does not exist in macrofunction "u0"

6 Replies
Altera_Forum
Honored Contributor II
4,534 Views

This error appears rather obvious - the port "pll_areset_conduit_export" does not exist in the u0 module. 

 

In future, I suggest you post your problems as text rather than images.
0 Kudos
Altera_Forum
Honored Contributor II
4,534 Views

ok, is it a syntax problem somewhere ? I cant figure it out . Ill try posting less images next time. sorry about the bandwidth burning

0 Kudos
Altera_Forum
Honored Contributor II
4,534 Views

Its not a syntax problem. The "cc_r2a_refdes_sdhc_cntrl_qsys" module does not have a port called pll_areset_conduit_export, but you are trying to connect pll_reset to it. did you forget to export it from your Qsys system, or did you get the name wrong?

0 Kudos
Altera_Forum
Honored Contributor II
4,534 Views

I am following a 60 something page tutorial pdf , I do not know why these seem to be missing?

0 Kudos
Altera_Forum
Honored Contributor II
4,534 Views

The problem is a very basic problem. 

You will need to check the Qsys system to ensure the missing port exists in the design.
0 Kudos
Altera_Forum
Honored Contributor II
4,534 Views

thanks again !

0 Kudos
Reply