FPGA to HPS and vice versa Communication for Cyclone V

[SanaGuezguez]

Hello everyone,

I'm having an issue implementing an FPGA to HPS communication and vice versa. I'm using the MitySOM 5csx with a Cyclone V SoC. The purpose of the project is to setup the bridges between the HPS and FPGA in such a way that a program running on the HPS will receive/send data from/to the FPGA. The data will be processed and the result will be returned back to the FPGA. I've generated a QSYS design, composed by the HPS (with Cyclone V settings), two fifos, a clock bridge, a clock and an SDRAM.
When I run the simulation and synthesis and the TCL pin-assignment script generated by Qsys everything works fine. The issue comes when I try to compile the whole design. I get an error message saying there are 375 IO input pads in the design, but only 331 IO input pad locations are available on the device.

I don't know what I'm missing or doing wrong. Any suggestion is welcome

[EBERLAZARE_I_Intel]

Hi,

Can you share your Quartus version that you are using? Also, can you attached/provide the exact errors that you are seeing when compiling in Quartus?

[SanaGuezguez]

Hi,

I'm using Quartus 17.1.
Here is the error : " Error (169281): There are 375 IO input pads in the design, but only 331 IO input pad locations available on the device. "

attached you can find 2 screenshots (part1 and part2) of  my QSYS design anf the vhd file for the pin instantiation.

[EBERLAZARE_I_Intel]

Hi,

Seems like it is a IO limitation issue in your design based on the board that you are using. There are too many IO input which is not supported which the device that you are using.

Firstly, can you re-check the Pin Planner to make sure the IO location assignments are set correctly.

Next, you could try to reduce the IO input pads in your design and recompile the design to see if that would work for your board.