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Help on project (DE2 Board)

Altera_Forum
Honored Contributor II
‎02-26-2011 05:17 AM
1,092 Views

Hey Friends, I am currently working on this Edge Extraction Project. 

 

I have the following components: Altera DE2(EP2C35) Board(NiosII, CycloneII). I need to do Edge Extraction. I get few errors running the program and I dont know how to correct it since I am poor in Verilog Coding. Somebody please debug this code and help me with my University Project pls... 

 

 

Reference and Design: 

http://people.ece.cornell.edu/land/courses/ece5760/finalprojects/f2007/hc454_gtc32/hc454_gtc32/index.html 

 

P.S: Attached the entire project, please debug the verilog module since i get a few errors, thank you
sobel.zip
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