Hi,
I am implementing an OpenRISC processor on a DE0-CV board which features a Cyclone-V FPGA. I am using Quartus Prime v19.1 Standard Edition.
In my design I instantiate an Altera PLL in order to generate 2 clocks, one for the processor and one for the SDRAM controller and the on-board SDRAM. The Processor clock I want it to be 120 MHz, while the clock for the controller and the SDRAM I want it to be 100 MHz.
I see that after Compilation, I have many Reg-to-Reg Setup violations (negative slack) and at the Timing Analyzer, the "report_clock_fmax_summary" reports the following maximum frequencies for those 2 clocks:
clk_120 --> 77.14 MHz
clk_100 --> 91.14 MHz
Does anyone know how accurate are those Maximum frequencies? Is this the Maximum that the design at its current state can reach without changing it on this specific FPGA? Is there anything that can be done to push for higher frequencies without changing the design?
Any answers or sources for reading will be welcome.
Looking forward for your response.
Kind regards,
anm
