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hi all,,
i have 2 problem with my verilog hdl coding. when i ran in quartus ii, it show:- 1. Error (10031): Net "sig_speed[15]" at pro_dec6.v(13) is already driven by input port "initial_speed[15]", and cannot be driven by another signal 2. Error (10032): "initial_speed[15]" was declared at pro_dec6.v(5) i also attach my verilog hdl. thanks.Link Copied
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Well it is what it says.
You are giving sig_speed[15] values from 2 different ports/signals. Somewhere in your code you have (this is VHDL code): something like this: sig_speed[15] <= example[15]; And somewhere else (maybe in a parallel proces) you have sig_speed[15]<=initial_speed[15]; Also your code isn't attached.- Mark as New
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The problem is exactly what have been told you by previous poster.
You're saying in code 2 different thing in different "process". You're saying 2 different thing and compiler of course do not know what you want: 1) when reset then out speed = fixed value, else set it at initial speed. always @(reset or initial_speed) begin if (reset == 1'b0) out_speed = 16'b0000000000000000; else sig_speed = initial_speed; <- THAT'S FIRST ASSIGNMENT end 2) In the following code you're saying a different thing always @ (clk or reset) begin if (reset == 1'b0) begin out_speed = 16'b0000000000000000; end else begin if (sig_speed == ref_speed) begin out_speed <= sig_speed; //out_speed <= initial_speed end else if (sig_speed < ref_speed) begin out_speed <= sig_speed; //sig_speed = 16'b0000000000000000; end else sig_speed <= sig_speed - 1; <- THAT'S THE SECOND ASSIGNMENT end end ---- If you think of what you're implement, code in part 1 is a ASYNCRONOUS MULTIPLEXER in which the reset signal is the selector. THe 2 input of this mux are : 1- Fixed value = 16'b0000000000000000; 2- the signal initial_speed There is no space for the counter you're instanciating in the second part of your code. I suppose that what you want to write is different and maybe is only the second part of your code or maybe it's initial_speed that you want to be decremented..- Mark as New
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that mean I need to do difference reg for both value..?
ps: Sorry,,, I'm beginner in verilog hdl thanks Darkwave and Thormodo- Mark as New
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No, what I mean is that you're doing a conceptual error.
Only 1 process can drive one signal.- Mark as New
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oooo,,ok... i understand that... tq very much....
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