How to handle Stratix10 HPS-to-FPGA bridge ID width mismatch

[seamusbleu]

The h2f_axi_master in the s10_hps has ID widths (AWID/ARID/RID/BID) of 4.  I connect it to my custom IP which also has an ID width of 4 but platform designer complains that the ID width must be 5.  I'm pretty sure that's because the h2f_axi_master is connected to the fpga_m2ocm_pb m0 bus. 

So my question is, can I increase the ID width on the s10_hps h2f_axi_master bus?  And if so, how? If not, how do I handle the mismatch?

This forum post suggests adding an AXI bridge.  But that doesn't work as the AXI bridge requires the ID widths on both sides be the same.

I also tried editing the s10 h2f_axi_master ID widths in platform designer from 4->3.  This seems to work, but when I create a build with this change, reads across the h2f_axi_master bus hang.  I'm guessing it has something to do with the read/write/combined issuing capability is set to 16, but needs to be changed to 8. 

Can someone tell me a good way around this issue?

[seamusbleu]

Link to HPS-to-FPGA Bridge showing ID width is 4.  This is also the case for the f2sdramN_data AXI slave buses.  I need to connect them up to 3 of my custom IP which also have master ID widths of 4.  In this case, I need the f2sdramN_data ID widths to go from 4->6 to accommodate the 3 masters.  So the above question(s) applies here as well.

[sstrell]

How do you have your addressing set up to each of the agents (slaves) the H2F bridge is connected to?  It's not shown in your screenshot.  And can you show the exact error/warning you are getting?

[seamusbleu]

CTRL_axi_master has id width of 6, REG_axi4_slave and DMA_axi_master have id width of 4.  There are 3 instances of the IP, thus the error message is that it wants me to add 2b to the s10_hps.f2sdram0_data slave axi bus that is connected to the CTRL_axi_master buses (same for the s10_hps.f2sdram1_data slave connected to the DMA_axi master buses).  The s10_hps.h2f_axi_master is connected to the fpga_m2ocm_pb master, thus it wants me to add 1b to the REG_axi4_slave (or subtract 1 from the s10_hps.h2f_axi_master).

[JingyangTeh]

Hi seamusbleu

I am Jingyang and I am was assigned to this case.

Please give me a moment to look into this issue and I will get back to you as soon as possible.

Regards

Jingyang, Teh

[JingyangTeh]

Hi seamusbleu

An update on this case, I am still working out internally with our team on the ID width mismatch issue.

I am trying to check if is there a way to change the bridge ID width from Quartus.

Regards

Jingyang, Teh

[JingyangTeh]

Hi seamusbleu

Is it possible if you could share the quartus design file to us?

Regards

Jingyang, Teh

[seamusbleu]

Do a "git clone https://github.com/altera-opensource/ghrd-socfpga.git ghrd-socfpga", then apply the changed files in the attached archive, then do a "make generate_from_tcl" and then "make quartus_edit", then open the qsys_top.qsys file and you will see the warnings shown above.

[JingyangTeh]

Hi

An update on this case.

We are still working on this case internally.

Sorry for the slow response.

Regards

Jingyang, Teh

[JingyangTeh]

Hi seamusblue

Sorry for the late reply.

How are you reading the through the h2f axi bus?

Could you share the method you are using to read the bus?

Regards

Jingyang, Teh

[seamusbleu]

I'm not sure how or why that is relevant to the question about how to handle ID width mismatches, but we read through the H2F bus via u-boot, or linux - does that answer your question?  I'd love to see an answer or some suggestions related to my question.

[JingyangTeh]

Hi seamusbleu

The reason behind the question before is to rule out any possibility.

I just got an advice from my senior that the AXI ID width of the HPS is not able to be changed.

As for the connection you have the hang is expected as the axi transactioin is exceeding the axi id value.

To solve the error in quartus, you could use the AXI bridge to connect the slaves and master together.

The mismatch in the AXI ID width is still be able to be connected but in the AXI transaction you will need to bare in mind to not exceed the maximum id value of the lesser ID width.

Regards

Jingyang, Teh

[seamusbleu]

Please show me how to use an AXI bridge to connect the slaves and masters together such that the ID widths can be different on the respective sides. 

As I stated in the original post:
>This forum post suggests adding an AXI bridge.  But that doesn't work as the AXI bridge requires the ID widths on both sides be the same.

[JingyangTeh]

Hi seamusbleu

Sorry for suggesting that idea.

It seems like that have added the checking of mismatch slave and master ID.

There was an update to the IP to add in this checking.

We could not change the slave id width of the HPS.

The checking of the slave id width is as follow:

Slave ID width = max master ID width + log2(number of masters)

One of two option is

1. To reduce the number of master connected.
2. To reduce the master id width connected to the slave.

Reducing the master id width to 2 you could connect up to 4 master to the slave.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[seamusbleu · Accepted solution]

So what you're saying is that there is no solution to this problem - that is not helpful.

[JingyangTeh]

Hi seamusbleu

Sorry that we could not change the AXI ID width of the HPS.

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh