How to make phase compensation between two clocks

[lambert_yu]

Hi all,

   fpga type : 10ax115n3f45i1sg

  quartus : quartus 18.0.0 standard

  I have one design as below:

    pll pll_inst(.rst(), .refclk(), .outclk1(), .outclk2(),.outclk3(),.outclk4());//the output clocks all use global clock routing.

    outclk1 = 2* outclk2; outclk2 = 2*outclk3; outclk3 = 2* outclk4;

    the output phase of these clk are all alignment (0 phase).

   clk_fast = sel = 2 ? outlck1 : sel = 1 ? outclk 2 : sel = 0 ? outclk3;

  clk_slow = sel = 2 ? outclk2 : sel = 1 ? outclk3 : sel = 0 ? outclk4;

  clk_buffer clk_buf_inst(.inclk(clk_fast), outclk(clk_fast_gl));//global

  clk_buffer clk_buf_inst1(.inclk(clk_slow),outclk(clk_slow_gl));//global

  Now there's transfer from A register (in clk_fast) to B register (in clk_slow).

   and there's transfer from C register (in clk_slow) to D register (in clk_fast).

  I made sdc constranins as follow:

   set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -setup -start 1

 set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -hold-end 1

set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -setup -start 1

set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -hold -end 1

 And all timing analisis all passed.

  But on board test, I found clk_fast_gl and clk_slow_gl could not keep phase align for some sel item. How could I make sure this point? Could you please provide some help about this?

BRs,

Lambert

[sstrell]

Where are the rest of your timing constraints that define the clocks themselves (create_clock, create_generated_clock, etc.)?

Also, a multicycle setup constraint of 1 does nothing because that's the default.  As such, a multicycle hold of 1 won't work correctly because it's supposed to be based off a setup multicycle.  Also, you've misspelled "multicycle" in all those constraints so I don't know if you copy/pasted this from your .sdc or just manually typed it.

Can you show more complete code or timing analyzer reports or timing waveforms of what you expect vs. what you are seeing?

[lambert_yu]

Hi, sstrell

   I'm sorry that I made you confusion.

   ///clock constrains:

     create_clock -name clk -periond 16.000 -waveform {0.000 8.000} [get_ports {clk}] -add

    create_clock -name clock_fast_gl -period 8.000 [get_pins {clock_buf_inst|altclkctrl_0|clock_buf_altclkctrl_180_76rtb7q_sub_component|sd1|outclk}]

   create_clock -name clock_slow_gl -period 16.000 [get_pins {clock_buf_inst|altclkctrl_0|clock_buf_altclkctrl_180_76rtb7q_sub_component|sd1|outclk}]

  derive_pll_clocks

 ///multicycle

set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -setup -start 1

 set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -hold-end 1

set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -setup -start 1

set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -hold -end 1

Yes, for setup items , it should use the default setup check. But for hold items, I made sure it make sense just from the timing analysis (as below figure).

/// fast to slow (setup)

 ///fast to slow (hold)

///slow to fast (setup)

///slow to fast (hold)

(From slow clock domain to fast clock domain, I think if the setup timing (from current launch clock edge to next latch clock edge) and hold timing (from current launch clock edge to previous latch clock edge ) are all satisfy, the setup and holdup timing for the current latch clock edge (which is located at between next latch edge and previous latch edge) will be satisfy.

The timing are all satisfy, but I don't know why clock_fast_gl and clock_slow_gl could not be keep in phase after altclkctrl IP.

If you need more information, you could tell me. Thanks!

BRs,

Lambert

[RichardTanSY_Altera]

You may use below multicycle constraints for fast-to-slow and slow-to-fast clock:

1) fast-to-slow clock :

set_multicycle_path -setup -from launch_clk(fast) -to latch_clock(slow) -start N

set_multicycle_path -hold -from launch_clk(fast) -to latch_clock(slow) -start N-1

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683243/24-1/source-clock-frequency-is-a-multiple-84878.html

2) slow-to-fast clock :

set_multicycle_path -setup -from launch_clk(slow) -to latch_clock(fast) -end N

set_multicycle_path -hold -from launch_clk(slow) -to latch_clock(fast) -end N-1

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683243/24-1/destination-clock-frequency-is-a-multiple-42731.html

When you specify a multicycle path with a value of 1, it essentially means that the timing path is expected to be completed within one clock cycle, which is the default behavior. 

Regards,

Richard Tan

[lambert_yu]

Hi, Richard

   For the constrains :

   set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -setup -start 1

   set_multicylce_path -from [get_clocks {clock_fast_gl}] -to [get_clocks [clock_slow_gl]} -hold-end 1

   set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -setup -start 1

   set_multicylce_path -from [get_clocks {clock_slow_gl}] -to [get_clocks [clock_fast_gl]} -hold -end 1

  I want to used to the below case

   fast-> slow

  slow -> fast

And in the previous email, I think the setup and holdup timing analysis follows the above multicycle path constrains.

1) But I don't know if it's enough or correct ? Besides, for the fast clock, there's 3 selection; and slow clock has 3 selection.

  fast clock: 100M/50M/25M; slow clock : 50M/25M/12.5M, they all comes from the same PLL output.

  fast_clock = sel == 2 ？ 100M : sel==1 ? 50M : 25M;

  slow_clock = sel == 2 ? 50M : sel == 1 ? 25M : 12.5M;

 use clkctrl IP, force fast_clock and slow clock use global clock routing.

  2) But from the result of synthesis, they can not keep the phase relationship between each other. For example, in the above picture, the phase between fast_clock and slow_clock aligns to each other. after synthesis, there's phase shift. How could I keep this or there's no solution? (I tried to use dynamic phase adjustment, but it's hard to find one setting to achieve my goal.

BRs,

Lambert

[TingJiangT_Intel]

Hi there, could you help upload your project for investigation? You can remove all RTL files for confidentiality but please make sure it can open timing analyzer and apply changes in other machines. Thanks

[TingJiangT_Intel]

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