How to program an ALTPLL_RECONFIG core?

[hans86]

Hi All,

I using the ALTPLL_RECONFIG core on a CycloneIV and it seems to work fine except that I can't seem to duplicate the initial state mif file settings.

When I simulate the core I get clk0=100MHz and clk1=400KHz, I then reconfigure the core using the initial state mif file setting and I get the correct clk0=100MHz but clk1=1.2MHz which is 3 times as high. The core reports:

#  clk0 :    C0 :  high = 3 (3) ,  low = 3 (2) ,  mode =  even (  odd) ,  phase tap = 0 (0)

#  clk1 :    C1 :  high = 250 (625) ,  low = 250 (625) ,  mode =  even ( even) ,  phase tap = 0 (0)

# unused :    C2 :  high = 256 (5) ,  low = 256 (5) ,  mode =  even ( even) ,  phase tap = 0 (0)

# unused :    C3 :  high = 256 (5) ,  low = 256 (5) ,  mode =  even ( even) ,  phase tap = 0 (0)

# unused :    C4 :  high = 256 (5) ,  low = 256 (5) ,  mode =  even ( even) ,  phase tap = 0 (0)

#    Charge Pump Current (bit setting) = 0 ( 0 )

#    Loop Filter Capacitor (bit setting) = 0 ( 0 )

#    Loop Filter Resistor (bit setting) = 27 ( 0 )

#    VCO_Post_Scale = 2 ( 2 )

What is confusing to me is the previous C1 value (in brackets) should be 625, how do I program 625 when the clk1 counter is only 8 bits? The initial mif file indicates a value of 250 which I used, so I must have missed a settings?

Here is part of the mif file:

-- MIF file representing initial state of PLL Scan Chain

--   Device Family: Cyclone IV E

   72  :  0; -- clk1 counter: Bypass = 0 (1 bit(s))

   73  :  1; -- clk1 counter: High Count = 250 (8 bit(s))

   74  :  1;

   75  :  1;

   76  :  1;

   77  :  1;

   78  :  0;

   79  :  1;

   80  :  0;

Thanks,

Hans.

[AnandRaj_S_Intel]

Hi Hans,

Check if .mif file is included in your Altera PLL Reconfig IP. Enable the mif streaming and give mif path.

Regards

Anand

[hans86]

Hi Anand,

Thanks for replying, I checked the mif file and it is definitely being read by the ALTPLL_RECONFIG core.

However, given that the (ALTPLL generated) mif file is loaded into the ALTPLL_RECONFIG core a single reconfig pulse should not change the clk0/cl1 values right? Unfortunately this is not the case, both clock signals change to different values.

I then used the read_param signal to read back the cached values after reset and all I get back is zeros for the N/M/clk0/clk1 counters. This is strange as I can see the mif values being loaded into an altsyncram4 block during simulation. If I use the read_param signal after I programmed the ALTPLL_CONFIG myself I get all the right values (the ones I programmed in) so the read back is working.

So my findings are that:

1) The ALTPLL generate mif file loaded into the ALTPLL_RECONFIG core does not give the same results as using the Quartus generated ALTPLL values.

2) You cannot read back the ALTPLL_RECONFIG cached values until you have programmed the core.

I am sure the first one is incorrect as CycloneIV is not new and many customers must have used the ALTPLL_RECONFIG core successfully but I can't make it work, any clue as to what is going on?

Thanks,

Hans.

[AnandRaj_S_Intel]

​Hi,

the (ALTPLL generated) mif file is loaded into the ALTPLL_RECONFIG core a single reconfig pulse should not change the clk0/cl1 values right? Unfortunately this is not the case, both clock signals change to different values.

>>Single pulse is enough to trigger the reconfiguration but clk0 and clk1 values will change after busy signal deassert.

1) The ALTPLL generate mif file loaded into the ALTPLL_RECONFIG core does not give the same results as using the Quartus generated ALTPLL values.

>>Do you mean mega-wizard generated mif is file is not working and Qsys generated mif file is working??

2) You cannot read back the ALTPLL_RECONFIG cached values until you have programmed the core.

>>Yes, You are correct.

Regards

Anand

[hans86]

Hi Anand,

Thanks for the follow up, I found the answer to my point 1, as described in the CycloneIV Device Handbook from 2016 it states:

Post-scale counter cascading is automatically set by the Quartus II software in the configuration file. Post-scale counter cascading cannot be performed using the PLL reconfiguration.

I was using the ALTPLL (Phase-Locked Loop) IP Core User Guide and the Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) IP Core User Guide both from 2017 neither mention this fact. It explains the C1 value of 625 which a user can't get to with an 8 bits register.

So the conclusion is that the values defined during Quartus IP configuration cannot all be reproduced using the ALTPLL_RECONFIG or with the mif file.

I think a warning during the ALTPLL configurations (when users click the dynamic configuration option and uses a too low frequency) would be very helpful.

Thanks for replying you did give me a good hint to investigate the mif file,

Thanks,

Hans.

[AnandRaj_S_Intel]

Hi Hans,

Thanks for sharing the information which will help the community.

Regards

Anand