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How to set timing constraint for JTAG

XQSHEN
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XQSHEN_0-1650714307626.png

 

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ak6dn
Valued Contributor III
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Here is how I put timing constraints on a JTAG interface (I do it in an .sdc constraint file):

 

# JTAG setup for Altera USB Blaster

set_false_path -from [get_ports {altera_reserved_*}] -to CPUCLK
set_false_path -from CPUCLK -to [get_ports {altera_reserved_*}]

create_clock -name altera_reserved_tck -period 40 {altera_reserved_tck}
remove_input_delay [get_ports {altera_reserved_tdi altera_reserved_tms}]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports {altera_reserved_tdi altera_reserved_tms}]
remove_output_delay [get_ports {altera_reserved_tdo}]
set_output_delay -clock altera_reserved_tck 3 [get_ports {altera_reserved_tdo}]

# Cut off paths between async clock domains

remove_clock_groups -all
set_clock_groups -asynchronous -group {CPUCLK} -group {altera_reserved_tck}

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ak6dn
Valued Contributor III
871 Views

Here is how I put timing constraints on a JTAG interface (I do it in an .sdc constraint file):

 

# JTAG setup for Altera USB Blaster

set_false_path -from [get_ports {altera_reserved_*}] -to CPUCLK
set_false_path -from CPUCLK -to [get_ports {altera_reserved_*}]

create_clock -name altera_reserved_tck -period 40 {altera_reserved_tck}
remove_input_delay [get_ports {altera_reserved_tdi altera_reserved_tms}]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports {altera_reserved_tdi altera_reserved_tms}]
remove_output_delay [get_ports {altera_reserved_tdo}]
set_output_delay -clock altera_reserved_tck 3 [get_ports {altera_reserved_tdo}]

# Cut off paths between async clock domains

remove_clock_groups -all
set_clock_groups -asynchronous -group {CPUCLK} -group {altera_reserved_tck}
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