How to verify timing for Agilex DDR4 Post Layout

[jaxbir267]

Hello, 

How do I verify that my layout is meeting timing requirements with Agilex 7 and a Quartus Prime Pro 24.1.0.115.

I am trying to verify that a DDR4 design meets timing requirements post-layout in Hyperlynx. I'm using an Agilex 7 and am not able to find anything in Quartus/EMIF User Guides that provide evidence that I'm able to do this accurately.

It appears that Intel no longer supports designers ability to do this as I'm not seeing evidence of a) Quartus exporting a timing report .v file nor do they b) import board characteristics (i.e skew/propagation delay) in the EMIF IP for timing analysis.

I am a novice at using Quartus so maybe I'm just missing something, any assistance is appreciated!

[sstrell]

You don't mention whether this is F, I or M-series, but here's the chapter on timing closure for F and I series: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/f-series-and-i-series-fpga-emif-ip-i.html

And for M-series: https://www.intel.com/content/www/us/en/docs/programmable/772538/24-3-1/m-series-fpga-emif-ip-timing-closure.html

And the DDR4 board design guidelines: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/ddr4-board-design-guidelines.html and https://www.intel.com/content/www/us/en/docs/programmable/772538/24-3-1/ddr4-board-design-guidelines.html.

Why would the timing report be generated as a Verilog (.v) file?

Since most of the IP is now completely hardened, you really have to rely on board simulations to guarantee your design as you have found.  Is something missing from the board design guidelines chapters that you are looking for?

[jaxbir267]

Hi, 

I am using an F-series Agilex part. The DDR4 will be running off both Fabric and HPS pins. 

That being said I have run into the timing closure chapter before but didn't find it useful particularly because I did not know how to export my design to touchstone file. After your response I have investigated further and found that Hyperlynx does export S-parameter files (yay!) but still need to investigate how to do it properly. Is there help on doing this?

I was hoping a .v file could be generated directly from the Quartus EMIF IP because that would allow me to do the timing analysis within Hyperlynx with their DDR analysis tool.

[jaxbir267]

Please provide guidance on how Intel recommends to perform timing closure analysis. I thought I would be able to use their DDRx Batch Mode Wizard but it is seeming increasingly that this is not what Intel intended.

I've now got SPICE models that are supposed to help me perform the timing Analysis, but the DDR simulation tool in Hyperlynx doesn't require SPICE models in order to run. Additionally I now have a .dat file that has timing spec information but don't know where to apply that either

I am new to this and am not finding sufficient guidance on how to verify my design based on the Design Guideline.

[AdzimZM_Intel · Accepted solution]

Hi,

Quartus no longer perform the timing analysis on DDR based on pcb characteristics for Agilex devices.

You should follow the routing guideline and skew matching guidelines from the UG.

• https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/single-rank-x-16-discrete-component-topology.html
• https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/skew-matching-guidelines-for-ddr4-discrete.html

Regards,

Adzim