- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ?
For my board,there is no input signal, how can I generate a internal reset ,can you give me a example for that ,or where I can find the reference?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can I use the locked output of pll to generate a reset signal for my design?
Yes , you can use it , but you have to be careful since when clock fails or skew or jitter or any issue related to the clock; PLL will lose it lock and it will reset your system.
what is the best reset mode for max10 ?
I am not following you , what you really menat by reset mode of max 10 ?
For my board,there is no input signal, how can I generate a internal reset ,can you give me a example for that ,or where I can find the reference?
Can you refer to your another post , I replied to that
https://forums.intel.com/s/question/0D50P00004YEdCR/i-do-not-have-the-input-reset-signal-from-the-outside-of-the-altera-fpgaand-want-to-generate-reset-internallycan-i-do-like-below-
Thank you,
Regards,
Sree
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Very simple to do. Init a register to '0' and have it drive the RESET~ signal (ie, an active low reset).
Then have a counter that starts at '0' and counts up for some number of bits (width depends on clock period and desired reset pulse width).
When the counter overflows (or hits some predetermined value) set the register driving RESET~ to a '1', which deasserts reset.
I have used this technique on various parts to, for example, generate a fixed 500ms reset pulse on FPGA powerup/configuration.
No external reset input signal required.
I used the onboard PLL to generate my system clock from the external 50MHz crystal oscillator input. I also used the 50MHz clock input to drive the reset generation logic (so it operates independent of the PLL).
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
oh,thanks very much!
what about use the output of the pll to driver the reset generation logic ?
Can the code below generate a reset correctly?
always@(posedge sys_clk ) //sys_clk is a output of the pll and is 200Mhz
begin
if(~locked_sig)
reset_cnt <= 30'd0;
else if(reset_cnt < 30'd200_000_005 ) // 1second to configure
reset_cnt <= reset_cnt + 30'd1;
end
assign rst_n = (reset_cnt == 30'd200_000_001)?1'b0:1'b1;
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Nope, I don't like that approach. Can't rely on SYS_CLK being valid if PLL is not locked.
Here is what I do. I generate an async reset at powerup ONLY. Sync to PLL clock via dual rank sync circuit if sync reset is desired instead.
// PowerUP Reset Logic
// generate a 500ms reset pulse on initial powerup
`ifdef SIMULATION
reg [24:0] pup_count = 25'd24999900;
`else
reg [24:0] pup_count = 25'd0;
`endif
reg pup_reset = 1'b1;
always @(posedge CLOCK_50)
begin
pup_count <= #TPD pup_count + 1'd1;
if (pup_count == 25'd25000000) pup_reset <= #TPD 1'b0;
end
wire reset = pup_reset;
PLL logic looks like this:
// Altera PLL Clock module
// Transform external crystal clock to our internal CPU clock
wire pll_locked;
wire CLOCK_CPU;
pll pll
( .inclk0 (CLOCK_50), // input clock
.locked (pll_locked), // status output
.c0 (CLOCK_CPU) // output clock
);
wire clk = CLOCK_CPU;
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sure ....but my only cocnern is what is the initial value of the counter register PUP_count ?
Thank you ,
Regards,
Sree
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
to intel engineer
the sys_clk is 200Mhz, and the initial value of the counter register is 30'd200_000_005 need about 1 second to count,
I want to know :
1) which implementation is better , ak6dn's(directly using the input clcok ) or mine ?
2)if using ak6dn's, and the pll has several output clocks, the asynchronously asserting and synchronously desserting must be done according to different clock domain,right ?
3) what is the intel oppion about that whether a input reset pin should be used or not ?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
To SREE: the initial value of PUP_COUNT is zero. Why is this a concern?
To ZLAN01: My logic generates an async reset signal which can be used to async reset registers in any clock domain. If you want a sync reset instead, just run the async reset thru a dual rank synchronizer for the specific clock domain. You may have just one, or possibly even more. So it depends on how you write your system logic (w/ async or sync reset).
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Usually it is good to know the state of register to the known value ; Can i know how to find the PUP_COUNT value once power ON and no clock fed to the sysytem ? I belive it is undefined in your case and clock started to fed counter will start from unknown value.
Also note : I am not saying this is going to happen but what i believe is there is chance it can happen.
Thank you,
Regards,
Sree
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
SREE,
This assignment statement in the above Verilog:
reg [24:0] pup_count = 25'd0;
sets the initial value of the PUP_COUNT register to zero. It does not require a clock, it is initialized from the POF file.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
SO, The enginner of intel means that the method giving 25'd0 to pup_count is not reliable ?
And the standard process for altera is to input a reset signal to the FPGA ?right ?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Honestly I don't know what Intel support person Sree is talking about. Maybe they misunderstand the issue.
I have assigned initial power up values to registers using the mechanism I illustrated for YEARS and it works just fine.
The reason to use an external reset signal input is if you want to reset the device state AFTER powerup configuration.
The value assignment to the register is only good after configuring the device (at powerup or anytime a reconfig is triggered).
If you want to do a device reset at an arbitrary time, and not have to force a device reconfiguration, an external reset signal is good for that.
And as I said I have no idea what Sree was referring to. His/her response is basically WRONG.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello all,
Sorry i was caught up into different stuff ,
Actually in synthesis world reg [24:0] pup_count = 25'd0; is doesnt mean anything. if you think how you infer this as hardware i am not sure how to design or i can say there should be some define state to make sure it is set to Logic 0 or 1.
I have to check the LRM and Quartus synthesis tool to confrim by deafult the state of the reg type signal.
Also reg [24:0] pup_count = 25'd0; only used in Simulation not use in synthesis.
Hence if you want your design have valid state at reset kindly consider to use external Reset.
Sorry delay in repsonse again.
Thank you,
Regards,
Sree
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sorry Intel support person Sree you are misinformed and do not know what you are talking about.
I have been using the construct reg [24:0] pup_count = 25'd0; for YEARS now in the Quartus synthesis tools (at least since 11.0sp1) to assign the default initial powerup configuration of a register.
Using the external reset pin to feed into the async reset of a register is NOT necessary. The above construct works just fine for an initial powerup configuration.
Using the async reset pin is ONLY necessary if you want to perform that function AFTER initial powerup configuration.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page