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I'm trying to set 8 bits of a register with 8 inputs, but I get an error "Can't resolve multiple constant drivers for net"


This is my first time writing any CPLD/FPGA code, specifically Verilog HDL. I'm trying to recreate the CD4021 parallel in serial out shift register.


Here is some of my code, A to H are all separate inputs.

It compiles fine, until I put it in my block diagram and connect A to H.

I get this error 'Can't resolve multiple constant drivers for net "register[(0 to 7)] at cd4021.v"', 8 times, once for each bit.


reg [7:0] register;       always @(posedge LATCH)   begin   index = 0;   register[0] <= A;   register[1] <= B;   register[2] <= C;   register[3] <= D;   register[4] <= E;   register[5] <= F;   register[6] <= G;   register[7] <= H;   end



Another quick question, why do I always see <= instead of just = in everyone else's code?

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Honored Contributor III

Why are you connecting A to H? If you do that, that could be the problem. Is there more code here or can you post your schematic? What's the index?


As for your second question, <= is used for non-blocking assignments usually used to define synchronous logic and < is used for blocking assignments, typically for combinatorial logic. See this online training for some Verilog basics:



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