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JJin01
Beginner
407 Views

I want to use external switching clock.. plz help

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My design need a external switching clock, which is an input clock that can externally reset its clock rate.

fpga1.jpg

 

I need to constrain this clock, but I don't know how to do it..

ryan scovil' timequest userguide or source synchronous guide doesn't show me the way to constraining this..

I think there's one way to do that, which is to use pll reconfig. The input clock will be the external clock and the c0 clock will use the same clock as the input clock. but is this the only way?

Let me know if there's any other way. THANK YOU

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1 Solution
sstrell
Honored Contributor II
74 Views

Are you saying that the input clock can be anything between 10 MHz and 300 MHz? If so, you'd probably want to constrain for the fastest clock (replace ext_clk with the name of your top-level clock port:

 

create_clock -name ext_clk -period 3.3 [get_ports ext_clk]

 

Then, if it's going through a PLL, just use:

 

derive_pll_clocks

 

#iwork4intel

View solution in original post

2 Replies
sstrell
Honored Contributor II
75 Views

Are you saying that the input clock can be anything between 10 MHz and 300 MHz? If so, you'd probably want to constrain for the fastest clock (replace ext_clk with the name of your top-level clock port:

 

create_clock -name ext_clk -period 3.3 [get_ports ext_clk]

 

Then, if it's going through a PLL, just use:

 

derive_pll_clocks

 

#iwork4intel

View solution in original post

JJin01
Beginner
74 Views

I understand, thank you!

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