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Integrating I2C slave to Avalon MM Master bridge

fedecive
Beginner
513 Views

Hi,

I am integrating the I2C slave to Avalon MM Master bridge IP inside my project for Cyclone 10 LP but it is still unclear how this IP works.

Here you can find the SignalTap attached to both I2C lanes and Avalon MM Master signals. From the host side I am sending the device address (0x55 selected in the qsys parameter of the IP), 4 byte address (0x0000000A) and one byte of data (0x01). Also considering 4 byte of data (0x00000001) the behavior is the same.

Screenshot from 2021-12-10 18-20-20.png

As you can see, the IP correctly acknowledges the master communication but the Avalon MM address and data are not correctly set, as well as the write signal.

In the following image, you can see the qsys settings for the I2C slave to Avalon MM Master bridge IP:

Screenshot from 2021-12-10 18-25-30.png

 

Which is the correct data that I have to send via I2C? I have to write the following data into the Avalon MM via I2C:

Avalon MM address: 0x0000000A

Avalon MM data to write: 0x00000001

Thank you.

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1 Solution
fedecive
Beginner
423 Views

Hi Sheng,

yes, I was able to resolve the issue. We can close the thread.

Thank you.

View solution in original post

3 Replies
sstrell
Honored Contributor III
495 Views

I'm not an I2C expert, but shouldn't the address you want to put on the Avalon bus (0xA) be in the second byte from I2C, not 4 bytes later?  I'm presuming the first byte is the control byte.  Are you following the Embedded Peripherals IP user guide (page 202 of the pdf)?:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

ShengN_Intel
Employee
428 Views

Hi fedecive,

 

Any update on this thread?

 

Best regards,
Sheng


fedecive
Beginner
424 Views

Hi Sheng,

yes, I was able to resolve the issue. We can close the thread.

Thank you.

Reply