LUT register mode for Stratix IV

[Altera_Forum]

Hi, 

 I have a extremely register rich design and will need to select a larger device.  I'm aware that the Stratix IV, or III, ALM has a LUT-register mode. Two LUTs can be configured as one register. The Stratix IV handbook says one ALM can contains three FFs, which means one LAB can contains up 30 FFs.  However, I failed to fit designs with only 21 FFs into one LAB. Does someone know how I can make it possible?  Regards

[Altera_Forum]

--- Quote Start ---  Hi,  I have a extremely register rich design and will need to select a larger device.  I'm aware that the Stratix IV, or III, ALM has a LUT-register mode. Two LUTs can be configured as one register. The Stratix IV handbook says one ALM can contains three FFs, which means one LAB can contains up 30 FFs.  However, I failed to fit designs with only 21 FFs into one LAB. Does someone know how I can make it possible?  Regards  --- Quote End ---    Hi gee,  what is your overall utilization of your device ? Did you try to optimize the design for area ?  Kind regards  GPK

[Altera_Forum]

Hi Pletz, 

 I appreciate your response. No, I didn't try because I'm just doing resource estimation and find the best device. However, it's shortage of FFs not logic, so I guess optimization won't solve it.  Regards

[Altera_Forum]

--- Quote Start ---  Hi Pletz,  I appreciate your response. No, I didn't try because I'm just doing resource estimation and find the best device. However, it's shortage of FFs not logic, so I guess optimization won't solve it.  Regards  --- Quote End ---    Hi Gee,  do you use memories in your design ? If yes, are all memories recognized and implemented in FPGA RAM resources ?   Kind regards  GPK

[Altera_Forum]

Hi pletz, 

 Yes. I tries to convert shift registers into RAM as much as possible in my resource estimation.  Regards

[Altera_Forum]

--- Quote Start ---  Hi pletz,  Yes. I tries to convert shift registers into RAM as much as possible in my resource estimation.  Regards  --- Quote End ---    Hi Gee,  here some ideas to "gain" some registers:  1. If you have input and output registers, use "Fast Input/Output Registers"  for the design input and outputs. This should force the fitter to use the FF's   in the I/O Cells.  2. Change your statemachine encoding for the project to "Minimal bits"  3. Change the setting for "Auto shift Register replacement" to "always"  Maybe your design will fit with the setting, but you should keep in mind that you run into trouble in case of design changes.  Kind regards  GPK

[Altera_Forum]

If I were to take a guess, the LUT_REG mapping algorithm is unaware of LogicLock regions. If you're running a test, make a shift register that has more registers than available in the device(and turn off the shift-reg replacement so they don't go into memories). I'll bet you see them get used. I have a number of designs with them. There is no fine-grained control though, i.e. synthesis sees it filling up and just starts converting non-timing critical registers to LUT_REGs. If I were to take a guess, there won't be much improvement on this since the SV architecture appears to have 4 registers in the ALM, and hence not much need for a LUT_REG.