Looking for Stratix 3 pin documentation

[Altera_Forum]

Hi, 

 I fail to find information on the DDR Input and Output register capabilities of the Stratix 3, L110 FPGA, device EP3SL110F1152C3.  I need to know whether a given pin has DDR capabilites. Can anyone point me to the place, where this is documented for a given chip in a given package?  Regards, flint

[Altera_Forum]

Ok, maybe we can solve the issue without documentation: I have a fit error with this message: 

 Error: Can't assign node "<design_top>|alt_iddr:\gen_dout:1:alt_iddr_3|altddio_in:altddio_in_component|ddio_in_sqi:auto_generated|ddio_ina[0]" to location IOPAD_X91_Y42_N0 -- node is type Double data rate I/O input circuitry  So I assume the Stratix 3 FPGA does not have DDR capabilities on this pin. Could there be another reason that Quartus can't fit this? If so, how could I find out about that.  Best regards flint

[Altera_Forum]

Ik, the problem was that I seemingly changed the location assignment of the input unintendedly in the assignment editor. So this was absolutely my mistake, sorry. 

 Best regards Matthias