MAX10 FPGA design : some questions about clock and other aspects

[Valerius]

Hi all,

finally I'm doing my first FPGA design (after tons with simpler CPLDs)
I'm targeting a MAX10 FPGA (10M08SCE144C8G is the exact part name).The design will be a kind of replacement installed on an old computer (mostly made with TTL logics).I have read the Intel® MAX® 10 guidelines and I want to feed the FPGA with a 6MHz clock signal coming from the old TTL hosting hardware.Should I simply connect this signal to one of the clock input of the MAX10 FPGA (for example pin 27 CLK0p like I did it in my schematics which I attach, it's missing the level shifters for proper 5V to 3.3VV translation though) or connect the signal to all 8 clock inputs CLK[3..0][p,n] so that they can drive all GCLK networks?Thanks in advance for any help or suggestion.

[sstrell]

You should only have to connect a single clock input but the user guide should help: https://www.intel.com/content/www/us/en/docs/programmable/683047/21-1/clocking-and-pll-overview.html

[RichardTanSY_Intel]

Hi,

You probably just need to connect the 6 MHz clock signal to one dedicated clock input pin rather than connecting it to all eight clock inputs to drive the global clock networks.

Let us know if you have further questions regarding this case.

Regards,

Richard Tan

[RichardTanSY_Intel]

Any update on this?

Do you need further help in regards to this case ?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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